[RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.
authorCraig Topper <craig.topper@sifive.com>
Wed, 20 Jan 2021 22:32:20 +0000 (14:32 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 20 Jan 2021 22:54:40 +0000 (14:54 -0800)
commit0f8386c4f6aa804fe43814fcb3ae29d271da82d7
tree0602ad78210834e04c89e89e4c3b2b542fe519a2
parent735a07f0478566f6f7c60a8a98eb8884db574113
[RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.

This is closer to the kind of code that these intrinsics are
targeted at. Note we fail to match slliu.w here because our pattern
looks for (and (shl X, C1), 0xffffffff << C1) rather than
(shl (and X, 0xffffffff), C1). I'll fix this in a follow up
commit.
llvm/test/CodeGen/RISCV/rv64Zbb.ll