WRITE_PORT_UCHAR((PUCHAR)0x71, value); \
})
-BOOLEAN MPSInitialized = FALSE; /* Is the MP system initialized? */
+static BOOLEAN MPSInitialized = FALSE; /* Is the MP system initialized? */
+static KDPC RescheduleDpc;
VOID APICDisable(VOID);
static VOID APICSyncArbIDs(VOID);
#endif /* MP */
-BOOLEAN BSPInitialized = FALSE; /* Is the BSP initialized? */
-
+static BOOLEAN BSPInitialized = FALSE; /* Is the BSP initialized? */
/* FUNCTIONS *****************************************************************/
PULONG Base;
Base = (PULONG)IOAPICMap[Apic].ApicAddress;
-
- *Base = Offset;
- return *((PULONG)((ULONG)Base + IOAPIC_IOWIN));
+ *Base = Offset;
+ return *((PULONG)((ULONG)Base + IOAPIC_IOWIN));
}
-
VOID IOAPICWrite(
ULONG Apic,
ULONG Offset,
PULONG Base;
Base = (PULONG)IOAPICMap[Apic].ApicAddress;
-
*Base = Offset;
- *((PULONG)((ULONG)Base + IOAPIC_IOWIN)) = Value;
+ *((PULONG)((ULONG)Base + IOAPIC_IOWIN)) = Value;
}
*/
memset(&Entry, 0, sizeof(Entry));
Entry.mask = 1;
+
IOAPICWrite(Apic, IOAPIC_REDTBL + 2 * Pin, *(((PULONG)&Entry) + 0));
IOAPICWrite(Apic, IOAPIC_REDTBL + 1 + 2 * Pin, *(((PULONG)&Entry) + 1));
}
*((PULONG)&Entry) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq);
Entry.mask = 1;
+
IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *((PULONG)&Entry));
}
*((PULONG)&Entry) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq);
Entry.mask = 0;
+
IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *((PULONG)&Entry));
}
tmp &= ~IOAPIC_ID_MASK;
tmp |= SET_IOAPIC_ID(IOAPICMap[apic].ApicId);
-
+
IOAPICWrite(apic, IOAPIC_ID, tmp);
/*
tmp = IOAPICRead(apic, 0);
if (GET_IOAPIC_ID(tmp) != IOAPICMap[apic].ApicId) {
DPRINT1("Could not set I/O APIC ID!\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
}
}
entry = irq_2_pin + entry->next;
if (++first_free_entry >= PIN_MAP_SIZE) {
DPRINT1("Ohh no!");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
}
entry->apic = apic;
static ULONG AssignIrqVector(
ULONG irq)
{
- static ULONG current_vector = FIRST_DEVICE_VECTOR, vector_offset = 0;
+ static ULONG current_vector = FIRST_DEVICE_VECTOR, vector_offset = 0;
ULONG vector;
/* There may already have been assigned a vector for this IRQ */
vector = IRQVectorMap[irq];
- if (vector > 0)
- return vector;
+ if (vector > 0)
+ return vector;
- current_vector += 8;
if (current_vector > FIRST_SYSTEM_VECTOR) {
- vector_offset++;
+ vector_offset++;
current_vector = FIRST_DEVICE_VECTOR + vector_offset;
} else if (current_vector == FIRST_SYSTEM_VECTOR) {
DPRINT1("Ran out of interrupt sources!");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
- IRQVectorMap[irq] = current_vector;
- return current_vector;
+ vector = current_vector;
+ IRQVectorMap[irq] = vector;
+ current_vector += 8;
+ return vector;
}
vector = AssignIrqVector(irq);
entry.vector = vector;
+ DPRINT("vector 0x%.08x assigned to irq 0x%.02x\n", vector, irq);
+
if (irq == 0)
{
/* Mask timer IRQ */
LONG Delta;
CurCount = Read8254Timer();
-
do {
PrevCount = CurCount;
CurCount = Read8254Timer();
/* Setup timer for normal operation */
//APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100); // 100ns
- APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 15000); // 15ms
- //APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100000); // 100ms
+// APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 15000); // 15ms
+ APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100000); // 100ms
DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
CPUMap[CPU].CoreSpeed/1000000,
{
#if 0
KIRQL OldIrql;
-#endif
- DPRINT("T1");
+ DPRINT("T:\n");
/*
- * Acknowledge the interrupt
+ * Notify the rest of the kernel of the raised irq level
*/
- APICSendEOI();
-#if 0
+ //OldIrql = KeRaiseIrqlToSynchLevel();
+ KeRaiseIrql(PROFILE_LEVEL, &OldIrql);
+
/*
- * Notify the rest of the kernel of the raised irq level
+ * Enable interrupts
+ * NOTE: Only higher priority interrupts will get through
*/
- OldIrql = KeRaiseIrqlToSynchLevel();
-#endif
__asm__("sti\n\t");
+ if (KeGetCurrentProcessorNumber() == 0)
+ {
+ //KIRQL OldIrql2;
+ //KeLowerIrql(PROFILE_LEVEL);
+ KiInterruptDispatch2(OldIrql, 0);
+ //KeRaiseIrql(CLOCK2_LEVEL, &OldIrql2);
+ }
+
+ DbgPrint("MpsTimerHandler() called at IRQL 0x%.08x\n", OldIrql);
+ //(BOOLEAN) KeInsertQueueDpc(&RescheduleDpc, NULL, NULL);
+
+ DbgPrint("MpsTimerHandler() -1 IRQL 0x%.08x\n", OldIrql);
+
/*
- * Call the dispatcher
+ * Disable interrupts
*/
- // TODO FIXME - What happened to definition for PsDispatchThread ???
- //PsDispatchThread(THREAD_STATE_READY);
+ __asm__("cli\n\t");
- // KeGetCurrentThread is linked into hal from ntoskrnl, so can
- // PsDispatchThread be exported from ntoskrnl also ???
+ DbgPrint("MpsTimerHandler() 0 IRQL 0x%.08x\n", OldIrql);
+ /*
+ * Acknowledge the interrupt
+ */
+ APICSendEOI();
-#if 0
/*
* Lower irq level
*/
+ DbgPrint("MpsTimerHandler() 1 IRQL 0x%.08x\n", OldIrql);
KeLowerIrql(OldIrql);
+ DbgPrint("MpsTimerHandler() 2 IRQL 0x%.08x\n", OldIrql);
#endif
}
{
DPRINT1("Spurious interrupt on CPU(%d)\n", ThisCPU());
- /*
- * Acknowledge the interrupt
- */
- APICSendEOI();
+ /* No need to send EOI here */
+
APICDump();
for (;;);
}
APICWrite(APIC_SIVR, tmp);
/*
- * Only the BP should see the LINT1 NMI signal, obviously.
+ * Only the BSP should see the LINT1 NMI signal, obviously.
*/
if (CPU == 0)
tmp = APIC_DM_NMI;
DPRINT("APIC found\n");
} else {
DPRINT1("No APIC found\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
CPUMap[BootCPU].MaxLVT = APICGetMaxLVT();
#ifdef MP
- return (NextCPU >= CPUCount);
+ //return (NextCPU >= CPUCount);
+ return (NextCPU >= 1);
#else /* MP */
DPRINT("Max # of I/O APICs (%d) exceeded (found %d).\n",
MAX_IOAPIC, IOAPICCount);
DPRINT1("Recompile with bigger MAX_IOAPIC!.\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
IOAPICMap[IOAPICCount].ApicId = m->ApicId;
IOAPICMap[IOAPICCount].ApicVersion = m->ApicVersion;
m->SrcBusIrq, m->DstApicId, m->DstApicInt);
if (IRQCount > MAX_IRQ_SOURCE) {
DPRINT1("Max # of irq sources exceeded!!\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
IRQMap[IRQCount] = *m;
*/
if ((m->IrqType == INT_EXTINT) && (m->DstApicLInt != 0)) {
DPRINT1("Invalid MP table!\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
if ((m->IrqType == INT_NMI) && (m->DstApicLInt != 1)) {
DPRINT1("Invalid MP table!\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
}
DbgPrint("Bad MP configuration block signature: %c%c%c%c\n",
pc[0], pc[1], pc[2], pc[3]);
- KeBugCheck(0);
+ KEBUGCHECK(0);
return;
}
if (MPChecksum((PUCHAR)Table, Table->Length))
{
DbgPrint("Bad MP configuration block checksum\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
return;
}
{
DbgPrint("Bad MP configuration table version (%d)\n",
Table->Specification);
- KeBugCheck(0);
+ KEBUGCHECK(0);
return;
}
{
DbgPrint("APIC base address is at 0x%X. " \
"I cannot handle non-standard adresses\n", APICBase);
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
Entry = (PUCHAR)((PVOID)Table + sizeof(MP_CONFIGURATION_TABLE));
}
default:
DbgPrint("Unknown entry in MPC table\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
}
}
}
}
+
BOOLEAN
HaliScanForMPConfigTable(
ULONG Base,
}
+static VOID STDCALL
+RescheduleDpcRoutine(PKDPC Dpc, PVOID DeferredContext,
+ PVOID SystemArgument1, PVOID SystemArgument2)
+{
+ KIRQL OldIrql;
+ KIRQL NewIrql;
+
+ DbgPrint("RDR()");
+ NewIrql = KeGetCurrentIrql();
+ KeLowerIrql(APC_LEVEL);
+ KeRescheduleThread();
+ KeRaiseIrql(NewIrql, &OldIrql);
+ DbgPrint("...\n");
+}
+
+
VOID
HalpInitMPS(
VOID)
MPSInitialized = TRUE;
+ KeInitializeDpc(&RescheduleDpc, RescheduleDpcRoutine, NULL);
+
/*
Scan the system memory for an MP configuration table
1) Scan the first KB of system base memory
EBDA <<= 4;
if (!HaliScanForMPConfigTable((ULONG)EBDA, 0x1000)) {
DbgPrint("No multiprocessor compliant system found.\n");
- KeBugCheck(0);
+ KEBUGCHECK(0);
}
}
}
}
/* Setup IRQ to vector translation map */
- memset(&IRQVectorMap, sizeof(IRQVectorMap), 0);
+ memset(&IRQVectorMap, 0, sizeof(IRQVectorMap));
/* Initialize the bootstrap processor */
HaliInitBSP();
git://git.jankratochvil.net / reactos.git / blobdiff