[TargetLowering] Only demand a rotation's modulo amount bits
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 17 Mar 2020 21:20:57 +0000 (21:20 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 17 Mar 2020 21:23:46 +0000 (21:23 +0000)
commit68224c19522220aa27bb0aee9e0f906c0d71f4f9
tree861b26fea7611b2bd5078e9833f258af31328d1c
parentc45eaeabb77a926f4f1cf3c1e9311e9d66e0ee2a
[TargetLowering] Only demand a rotation's modulo amount bits

ISD::ROTL/ROTR rotation values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits.

Differential Revision: https://reviews.llvm.org/D76201
12 files changed:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
llvm/test/CodeGen/PowerPC/rotl-2.ll
llvm/test/CodeGen/SystemZ/rot-01.ll
llvm/test/CodeGen/SystemZ/rot-02.ll
llvm/test/CodeGen/SystemZ/shift-04.ll
llvm/test/CodeGen/SystemZ/shift-08.ll
llvm/test/CodeGen/Thumb2/thumb2-ror.ll
llvm/test/CodeGen/X86/combine-rotates.ll
llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
llvm/test/CodeGen/X86/vector-fshr-rot-512.ll