5 years ago[StatepointsForGC] Rematerialize in the presence of PHIs
Anna Thomas [Mon, 29 Aug 2016 15:41:59 +0000 (15:41 +0000)]
[StatepointsForGC] Rematerialize in the presence of PHIs

While walking the use chain for identifying rematerializable values in RS4GC,
add the case where the current value and base value are the same PHI nodes.

This will aid rematerialization of geps and casts instead of relocating.

Reviewers: sanjoy, reames, igor

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23920

llvm-svn: 279975

5 years ago[LTO] Remove extraneous output
Teresa Johnson [Mon, 29 Aug 2016 15:33:01 +0000 (15:33 +0000)]
[LTO] Remove extraneous output

Remove some debugging output to stderr that snuck in with r279576.

llvm-svn: 279974

5 years ago[Constant] remove fdiv and frem from canTrap()
Sanjay Patel [Mon, 29 Aug 2016 15:27:17 +0000 (15:27 +0000)]
[Constant] remove fdiv and frem from canTrap()

Assuming the default FP env, we should not treat fdiv and frem any differently in terms of
trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env.

This matches how we treat the fdiv/frem in IR with isSafeToSpeculativelyExecute() and in
the backend after:

llvm-svn: 279973

5 years ago[SimplifyCFG] rename test file, regenerate checks, and add test
Sanjay Patel [Mon, 29 Aug 2016 14:57:53 +0000 (14:57 +0000)]
[SimplifyCFG] rename test file, regenerate checks, and add test

The fdiv test shows a problem similar to:

llvm-svn: 279972

5 years ago[Coroutines] Part 9: Add cleanup subfunction.
Gor Nishanov [Mon, 29 Aug 2016 14:34:12 +0000 (14:34 +0000)]
[Coroutines] Part 9: Add cleanup subfunction.

[Coroutines] Part 9: Add cleanup subfunction.

This patch completes coroutine heap allocation elision. Now, the heap elision example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex3.ll)

Intrinsic Changes:
* coro.free gets a token parameter tying it to coro.id to allow reliably discovering all coro.frees associated with a particular coroutine.
* coro.id gets an extra parameter that points back to a coroutine function. This allows to check whether a coro.id describes the enclosing function or it belongs to a different function that was later inlined.

CoroSplit now creates three subfunctions:
# f$resume - resume logic
# f$destroy - cleanup logic, followed by a deallocation code
# f$cleanup - just the cleanup code

CoroElide pass during devirtualization replaces coro.destroy with either f$destroy or f$cleanup depending whether heap elision is performed or not.

Other fixes, improvements:
* Fixed buglet in Shape::buildFrame that was not creating coro.save properly if coroutine has more than one suspend point.

* Switched to using variable width suspend index field (no longer limited to 32 bit index field can be as little as i1 or as large as i<whatever-size_t-is>)

Reviewers: majnemer

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D23844

llvm-svn: 279971

5 years ago[TargetLowering] remove fdiv and frem from canOpTrap() (PR29114)
Sanjay Patel [Mon, 29 Aug 2016 13:32:41 +0000 (13:32 +0000)]
[TargetLowering] remove fdiv and frem from canOpTrap() (PR29114)

Assuming the default FP env, we should not treat fdiv and frem any differently in terms of
trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env.

This matches how we treat these ops in IR with isSafeToSpeculativelyExecute(). There's a
similar bug in Constant::canTrap().

This bug manifests in PR29114:
...as a sequence of scalar divisions instead of a vector division on x86 for a <3 x float>

Differential Revision: https://reviews.llvm.org/D23974

llvm-svn: 279970

5 years agoDo not use MRI::getMaxLaneMaskForVReg as a mask covering whole register
Krzysztof Parzyszek [Mon, 29 Aug 2016 13:15:35 +0000 (13:15 +0000)]
Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole register

MRI::getMaxLaneMaskForVReg does not always cover the whole register.
For example, on X86 the upper 16 bits of EAX cannot be accessed via
any subregister. Consequently, there is no lane mask that only covers
that part of EAX. The getMaxLaneMaskForVReg will return the union of
the lane masks for all subregisters, and in case of EAX, that union
will not cover the upper 16 bits.

This fixes https://llvm.org/bugs/show_bug.cgi?id=29132

llvm-svn: 279969

5 years agoAMDGPU/SI: Improve register allocation hints for sopk instructions
Tom Stellard [Mon, 29 Aug 2016 13:06:10 +0000 (13:06 +0000)]
AMDGPU/SI: Improve register allocation hints for sopk instructions

For shrinking SOPK instructions, we were creating a hint to tell the
register allocator to use the register allocated for src0 for the dst
operand as well.  However, this seems to not work sometimes depending
on the order virtual registers are assigned physical registers.

To fix this, I've added a second allocation hint which does the reverse,
asks that the register allocated for dst is used for src0.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D23862

llvm-svn: 279968

5 years agoUse the correct ctor/dtor section for dynamic-no-pic.
Rafael Espindola [Mon, 29 Aug 2016 12:47:22 +0000 (12:47 +0000)]
Use the correct ctor/dtor section for dynamic-no-pic.

llvm-svn: 279967

5 years agoMark test as XFAIL instead of disabling it everywhere.
Benjamin Kramer [Mon, 29 Aug 2016 12:41:32 +0000 (12:41 +0000)]
Mark test as XFAIL instead of disabling it everywhere.

There is no lit feature 'X86' so this test is just disabled completely.
Make it XFAIL until a solution is found.

llvm-svn: 279966

5 years agoMove code only used by codegen out of MC. NFC.
Rafael Espindola [Mon, 29 Aug 2016 12:33:42 +0000 (12:33 +0000)]
Move code only used by codegen out of MC. NFC.

MC itself never needs to know about these sections.

llvm-svn: 279965

5 years agoFix -Wunused-but-set-variable warning.
Haojian Wu [Mon, 29 Aug 2016 12:26:33 +0000 (12:26 +0000)]
Fix -Wunused-but-set-variable warning.

Summary: A follow-up fix on r279958.

Reviewers: bkramer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D23989

llvm-svn: 279964

5 years agoAMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()
Tom Stellard [Mon, 29 Aug 2016 12:05:32 +0000 (12:05 +0000)]
AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()

The SILoadStoreOptimizer will need to use AliasAnalysis here in order to
move it before scheduling.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D23813

llvm-svn: 279963

5 years ago[Coverage] Prevent creating a redundant counter if a nested body ends with a macro.
Igor Kudrin [Mon, 29 Aug 2016 11:48:50 +0000 (11:48 +0000)]
[Coverage] Prevent creating a redundant counter if a nested body ends with a macro.

If there were several nested statements arranged in a way that all of them
end up with the same macro, then the expansion of this macro was assigned
with all the corresponding counters of these statements.
As a result, the wrong counter value was shown for the macro in llvm-cov.

This patch fixes the issue by preventing adding a counter for an expanded
source range if it already has an assigned counter, which is expected
to come from the most specific statement.

Differential Revision: https://reviews.llvm.org/D23160

llvm-svn: 279962

5 years agoFixed a bug in type legalizer for masked gather.
Igor Breger [Mon, 29 Aug 2016 09:12:31 +0000 (09:12 +0000)]
Fixed a bug in type legalizer for masked gather.
The problem occurs when the Node doesn't updated in place , UpdateNodeOperation() return the node that already exist.
In this case assert fail in PromoteIntegerOperand() , N have 2 results ( val + chain).

Differential Revision: http://reviews.llvm.org/D23756

llvm-svn: 279961

5 years ago[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence.
Igor Breger [Mon, 29 Aug 2016 08:52:52 +0000 (08:52 +0000)]
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence.

Differential Revision: http://reviews.llvm.org/D23490

llvm-svn: 279960

5 years ago[InstructionSelect] NumBlocks isn't defined in DEBUG build.
Haojian Wu [Mon, 29 Aug 2016 08:48:15 +0000 (08:48 +0000)]
[InstructionSelect] NumBlocks isn't defined in DEBUG build.

Summary: A follow-up fixing on http://llvm.org/viewvc/llvm-project?view=revision&revision=279905.

Reviewers: bkramer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D23985

llvm-svn: 279959

5 years ago[X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just create...
Craig Topper [Mon, 29 Aug 2016 04:49:31 +0000 (04:49 +0000)]
[X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just create a ConstantFPSDNode and let that be lowered.

This allows broadcast loads to used when available.

llvm-svn: 279958

5 years ago[AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to integer...
Craig Topper [Mon, 29 Aug 2016 04:49:27 +0000 (04:49 +0000)]
[AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to integer operations when DQI isn't supported. This is consistent with the recent changes to promote logical operations to i64 vectors.

llvm-svn: 279957

5 years ago[AVX-512] Add 512-bit fabs tests with and without AVX512DQ.
Craig Topper [Mon, 29 Aug 2016 04:49:24 +0000 (04:49 +0000)]
[AVX-512] Add 512-bit fabs tests with and without AVX512DQ.

llvm-svn: 279956

5 years agoFix pair::operator=(TupleLike&&).
Eric Fiselier [Mon, 29 Aug 2016 01:43:41 +0000 (01:43 +0000)]
Fix pair::operator=(TupleLike&&).

This assignment operator was previously broken since the SFINAE always resulted
in substitution failure. This caused assignments to turn into
copy construction + assignment.

This patch was originally committed as r279953 but was reverted due to warnings
in the test-suite. This new patch corrects those warnings.

llvm-svn: 279955

5 years agoRevert r279953 - Fix pair::operator=(TupleLike&&)
Eric Fiselier [Mon, 29 Aug 2016 01:39:54 +0000 (01:39 +0000)]
Revert r279953 - Fix pair::operator=(TupleLike&&)

The test emits warnings causing the test-suite to fail. Since I want this
patch merged into 3.9 I'll recommit it with a clean test.

llvm-svn: 279954

5 years agoFix pair::operator=(TupleLike&&).
Eric Fiselier [Mon, 29 Aug 2016 01:09:47 +0000 (01:09 +0000)]
Fix pair::operator=(TupleLike&&).

This assignment operator was previously broken since the SFINAE always resulted
in substitution failure. This caused assignments to turn into
copy construction + assignment.

llvm-svn: 279953

5 years ago[Orc] Simplify LogicalDylib and move it back inside CompileOnDemandLayer. Also
Lang Hames [Mon, 29 Aug 2016 00:54:29 +0000 (00:54 +0000)]
[Orc] Simplify LogicalDylib and move it back inside CompileOnDemandLayer. Also
switch to using one indirect stub manager per logical dylib rather than one per
input module.

LogicalDylib is a helper class used by the CompileOnDemandLayer to manage
symbol resolution between modules during lazy compilation. In particular, it
ensures that internal symbols resolve correctly even in the case where multiple
input modules contain the same internal symbol name (which must to be promoted
to external hidden linkage so that functions in any given module can be split
out by lazy compilation). LogicalDylib's resolution scheme (before this commit)
required one stub-manager per input module. This made recompilation of functions
(by adding a module containing a new definition) difficult, as the stub manager
for any given symbol was bound to the module that supplied the original
definition. By using one stubs manager for the whole logical dylib symbols can
be more easily replaced, although support for doing this is not included in this
patch (it will be implemented in a follow up).

llvm-svn: 279952

5 years ago[AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.
Craig Topper [Sun, 28 Aug 2016 22:20:51 +0000 (22:20 +0000)]
[AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.

llvm-svn: 279951

5 years ago[AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS instructions.
Craig Topper [Sun, 28 Aug 2016 22:20:48 +0000 (22:20 +0000)]
[AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS instructions.

llvm-svn: 279950

5 years ago[AVX-512] Add testcases showing that we don't emit 512-bit vpabsb/vpabsw. Will be...
Craig Topper [Sun, 28 Aug 2016 22:20:45 +0000 (22:20 +0000)]
[AVX-512] Add testcases showing that we don't emit 512-bit vpabsb/vpabsw. Will be fixed in a future commit.

llvm-svn: 279949

5 years agoImplement C++17 std::sample.
Eric Fiselier [Sun, 28 Aug 2016 22:14:37 +0000 (22:14 +0000)]
Implement C++17 std::sample.

This patch implements the std::sample function added to C++17 from LFTS. It
also removes the std::experimental::sample implementation which now forwards
to std::sample.

llvm-svn: 279948

5 years agoMark LWG 2716 as complete - shuffle and sample disallows lvalue URNGs.
Eric Fiselier [Sun, 28 Aug 2016 21:55:00 +0000 (21:55 +0000)]
Mark LWG  2716 as complete - shuffle and sample disallows lvalue URNGs.

Libc++'s implementation of shuffle and sample already support lvalue and rvalue
RNG's. This patch adds tests for both categories and marks the issue as complete.

This patch also contains drive-by change for std::experimental::sample which
improves the diagnostics produced when the correct iterator categories are
not supplied.

llvm-svn: 279947

5 years agoAST: improve layout of SimpleTypoCorrector
Saleem Abdulrasool [Sun, 28 Aug 2016 21:33:30 +0000 (21:33 +0000)]
AST: improve layout of SimpleTypoCorrector

Add the "explicit" specifier to the single-argument constructor of
SimpleTypoCorrector.  Reorder the fields to remove excessive padding (8 bytes).

Patch by Alexander Shaposhnikov!

llvm-svn: 279946

5 years agoImplement LWG 2711. Constrain path members.
Eric Fiselier [Sun, 28 Aug 2016 21:26:01 +0000 (21:26 +0000)]
Implement LWG 2711. Constrain path members.

llvm-svn: 279945

5 years agoFix some typos in the doc
Sylvestre Ledru [Sun, 28 Aug 2016 20:33:42 +0000 (20:33 +0000)]
Fix some typos in the doc

llvm-svn: 279944

5 years agoFix some typos in the doc
Sylvestre Ledru [Sun, 28 Aug 2016 20:29:18 +0000 (20:29 +0000)]
Fix some typos in the doc

llvm-svn: 279943

5 years agoFix a typo in the doc: overriden -> overridden
Sylvestre Ledru [Sun, 28 Aug 2016 20:22:34 +0000 (20:22 +0000)]
Fix a typo in the doc: overriden -> overridden

llvm-svn: 279942

5 years agoEHABI: fail on WMMX vops without WMMX support
Saleem Abdulrasool [Sun, 28 Aug 2016 20:10:33 +0000 (20:10 +0000)]
EHABI: fail on WMMX vops without WMMX support

When the unwinder is built without WMMX support, if we encounter a WMMX register
virtual operation, early rather than attempting to continue as we would not have
saved the register set anyways.  This should never come down this path, but,
just in case, help it abort more explicitly.

llvm-svn: 279941

5 years ago[Docs] Update libc++ target names after r279675.
Eric Fiselier [Sun, 28 Aug 2016 18:33:08 +0000 (18:33 +0000)]
[Docs] Update libc++ target names after r279675.

llvm-svn: 279940

5 years ago[x86] add tests for <3 x N> vector types (PR29114)
Sanjay Patel [Sun, 28 Aug 2016 18:31:32 +0000 (18:31 +0000)]
[x86] add tests for <3 x N> vector types (PR29114)

llvm-svn: 279939

5 years ago[CMake] Be more consistent about naming targets and components in libc++abi
Eric Fiselier [Sun, 28 Aug 2016 18:28:51 +0000 (18:28 +0000)]
[CMake] Be more consistent about naming targets and components in libc++abi

This patch (and commit summary) mirror r279675 by Chris B which was applied
to libc++ but not libc++abi.

The point of this patch is to have a consistent convention for naming build,
check and install targets so that the targets can be constructed from the
project name.

This change renames a bunch of CMake components and targets from libcxxabi to
cxxabi. For each renamed target I've added a convenience target that matches
the old target name and depends on the new target. This will preserve function
of the old targets so that the change doesn't break the world. We can evaluate
if it is worth removing the extra targets later.

llvm-svn: 279938

5 years ago[InstCombine] use m_APInt to allow icmp (and X, Y), C folds for splat constant vectors
Sanjay Patel [Sun, 28 Aug 2016 18:18:00 +0000 (18:18 +0000)]
[InstCombine] use m_APInt to allow icmp (and X, Y), C folds for splat constant vectors

llvm-svn: 279937

5 years ago[CMake] Apply r279151 cleanup to libc++abi.
Eric Fiselier [Sun, 28 Aug 2016 18:16:18 +0000 (18:16 +0000)]
[CMake] Apply r279151 cleanup to libc++abi.

This patch applies changes similar to those in r279515 to libc++abi.

Summary of changes in this patch:

* Renamed variable LLVM_CONFIG -> LLVM_CONFIG_PATH
* Add an include of AddLLVM in the tests subdirectory for add_lit_testsuite.

llvm-svn: 279936

5 years agotest: fix test under ASAN and MSAN
Saleem Abdulrasool [Sun, 28 Aug 2016 18:16:00 +0000 (18:16 +0000)]
test: fix test under ASAN and MSAN

When we're running tests under ASAN or MSAN, they're compiled with -O1, which
enables tail call elimination. This causes backtrace_test to fail: the compiler
performs tail call elimination for call3_nothrow, but it can't for call3_throw,
leading to a mismatched frame count. Disable tail call elimination (and
inlining, just to be explicit) to avoid this.

Patch by Shoaib Meenai!

llvm-svn: 279935

5 years ago[X86][AVX512] Only combine EVEX targets shuffles to shuffles of the same number of...
Simon Pilgrim [Sun, 28 Aug 2016 17:27:14 +0000 (17:27 +0000)]
[X86][AVX512] Only combine EVEX targets shuffles to shuffles of the same number of vector elements

Over eager combing prevents the correct folding of writemasks.

At the moment this occurs for ALL EVEX shuffles, in the future we need to check that the user of the root shuffle is a VSELECT that can fold to a writemask.

llvm-svn: 279934

5 years ago[PowerPC] Implement lowering for atomicrmw min/max/umin/umax
Hal Finkel [Sun, 28 Aug 2016 16:17:58 +0000 (16:17 +0000)]
[PowerPC] Implement lowering for atomicrmw min/max/umin/umax

Implement lowering for atomicrmw min/max/umin/umax. Fixes PR28818.

llvm-svn: 279933

5 years agoRevert "Start reifying error descriptions. Second try: Try to appease Visual Studio."
Filipe Cabecinhas [Sun, 28 Aug 2016 10:42:21 +0000 (10:42 +0000)]
Revert "Start reifying error descriptions. Second try: Try to appease Visual Studio."

This reverts r279931. Will try it with the same Visual Studio version
before committing again.

llvm-svn: 279932

5 years agoStart reifying error descriptions. Second try: Try to appease Visual Studio.
Filipe Cabecinhas [Sun, 28 Aug 2016 10:32:44 +0000 (10:32 +0000)]
Start reifying error descriptions. Second try: Try to appease Visual Studio.

This commit sets up the infrastructure to use reified error
descriptions, and moves ReportStackOverflow to the new system.

After we convert all the errors, we'll be able to simplify ScopedInErrorReport
and remove the older debugging mechanism which had some errors partly reified
in some way. We'll be able to maintain the external API.

ScopedInErrorReport will be able to track one of the reified errors at a time.
The purpose of this is so we have its destructor actually print the error and
possibly interface with the debugger (will depend on the platform, of course).

Reviewers: kcc, samsonov, timurrrr

Subscribers: kubabrecka, llvm-commits

Differential Revision: https://reviews.llvm.org/D23672

llvm-svn: 279931

5 years ago[Loop Vectorizer] Fixed memory confilict checks.
Elena Demikhovsky [Sun, 28 Aug 2016 08:53:53 +0000 (08:53 +0000)]
[Loop Vectorizer] Fixed memory confilict checks.

Fixed a bug in run-time checks for possible memory conflicts inside loop.
The bug is in Low <-> High boundaries calculation. The High boundary should be calculated as "last memory access pointer + element size".

Differential revision: https://reviews.llvm.org/D23176

llvm-svn: 279930

5 years ago[AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/AVX512VL.
Craig Topper [Sun, 28 Aug 2016 06:06:28 +0000 (06:06 +0000)]
[AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/AVX512VL.

Previously we weren't creating masked logical operations if bitcasts appeared between the logic operation and the select. The IR optimizers can move bitcasts across logic operations and create these cases. To minimize the number of cases we need to handle, this change promotes all logic ops to an i64 vector type just like when only SSE or AVX is available.

Unfortunately, this also has the consequence of making it difficult to select unmasked VPANDD/VPORD/VPXORD in all the cases it was previously used. This is the cause of most of the test change. This shouldn't result in any functional change though.

llvm-svn: 279929

5 years ago[AVX-512] Add tests to show that we don't select masked logic ops if there are bitcas...
Craig Topper [Sun, 28 Aug 2016 06:06:24 +0000 (06:06 +0000)]
[AVX-512] Add tests to show that we don't select masked logic ops if there are bitcasts between the logic op and the select.

This is taken from optimized IR of clang test cases for masked logic ops.

llvm-svn: 279928

5 years ago[X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instructions instea...
Craig Topper [Sun, 28 Aug 2016 06:06:21 +0000 (06:06 +0000)]
[X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instructions instead of ending 128/256. NFC

llvm-svn: 279927

5 years agoAvoid embedded preprocessor directives in __tree
Dimitry Andric [Sat, 27 Aug 2016 19:32:03 +0000 (19:32 +0000)]
Avoid embedded preprocessor directives in __tree

Similar to rL242623, move C++ version checks outside of _NOEXCEPT_()
macro invocation argument lists, to avoid "embedding a directive within
macro arguments has undefined behavior" warnings.

Differential Revision: https://reviews.llvm.org/D23961

llvm-svn: 279926

5 years agoAMDGPU/R600: Enable Load combine
Jan Vesely [Sat, 27 Aug 2016 19:09:43 +0000 (19:09 +0000)]
AMDGPU/R600: Enable Load combine

Fix and improve tests

Differential Revision: https://reviews.llvm.org/D23899

llvm-svn: 279925

5 years ago[X86] Rename predicate function that detects if requires one of the REX.B, REX.X...
Craig Topper [Sat, 27 Aug 2016 17:13:43 +0000 (17:13 +0000)]
[X86] Rename predicate function that detects if requires one of the REX.B, REX.X or REX.R bits. It's old name conflicted with a function in X8II namespace that doesnt' quite do the same thing. NFC

llvm-svn: 279924

5 years ago[X86] Keep looping over operands looking for byte registers even if we already found...
Craig Topper [Sat, 27 Aug 2016 17:13:41 +0000 (17:13 +0000)]
[X86] Keep looping over operands looking for byte registers even if we already found a register that requires a REX prefix. Otherwise we don't error if a high byte register is used after SPL/BPL/DIL/SIL.

llvm-svn: 279923

5 years ago[X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. This feels more consist...
Craig Topper [Sat, 27 Aug 2016 17:13:37 +0000 (17:13 +0000)]
[X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. This feels more consistent with its name and simplifies assembler code.

llvm-svn: 279922

5 years ago[X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8...
Craig Topper [Sat, 27 Aug 2016 17:13:34 +0000 (17:13 +0000)]
[X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15.

llvm-svn: 279921

5 years agoFix some build bot breakages.
Zachary Turner [Sat, 27 Aug 2016 16:38:11 +0000 (16:38 +0000)]
Fix some build bot breakages.

There was some code that was ifdef'ed out that I didn't catch
in my earlier patch.

llvm-svn: 279920

5 years agoAdd some unit tests for StringExtractor::GetNameColonValue.
Zachary Turner [Sat, 27 Aug 2016 16:35:15 +0000 (16:35 +0000)]
Add some unit tests for StringExtractor::GetNameColonValue.

These are helpful on their own, but will be even more useful
once the GetNameColonValue is updated to return StringRefs
instead of std::strings.

llvm-svn: 279919

5 years ago[asan] Disable tests more selectively.
Akira Hatanaka [Sat, 27 Aug 2016 16:06:36 +0000 (16:06 +0000)]
[asan] Disable tests more selectively.

Add "target-arch+host-os" to the feature list to enable disabling the
tests I committed in r279614 and r279880 more selectively.

llvm-svn: 279918

5 years agoConvert some functions to use StringRef instead of c_str, len
Zachary Turner [Sat, 27 Aug 2016 15:52:29 +0000 (15:52 +0000)]
Convert some functions to use StringRef instead of c_str, len

This started as an effort to change StringExtractor to store a
StringRef internally instead of a std::string.  I got that working
locally with just 1 test failure which I was unable to figure out the
cause of.  But it was also a massive changelist due to a trickle
down effect of changes.

So I'm starting over, using what I learned from the first time to
tackle smaller, more isolated changes hopefully leading up to
a full conversion by the end.

At first the changes (such as in this CL) will seem mostly
a matter of preference and pointless otherwise.  However, there
are some places in my larger CL where using StringRef turned 20+
lines of code into 2, drastically simplifying logic.  Hopefully
once these go in they will illustrate some of the benefits of
thinking in terms of StringRef.

llvm-svn: 279917

5 years ago[asan] Use "REQUIRES: x86_64-target-arch" to disable the test on i386.
Akira Hatanaka [Sat, 27 Aug 2016 05:57:50 +0000 (05:57 +0000)]
[asan] Use "REQUIRES: x86_64-target-arch" to disable the test on i386.

My attempt to disable this test on i386 by adding "UNSUPPORTED: i386-apple"
in r279880 wasn't succesful, so I'm using REQUIRES instead.

llvm-svn: 279916

5 years ago[X86] Remove stale comment about FixupBWInsts pass being off by default. NFC
Craig Topper [Sat, 27 Aug 2016 05:26:54 +0000 (05:26 +0000)]
[X86] Remove stale comment about FixupBWInsts pass being off by default. NFC

llvm-svn: 279915

5 years ago[AVX-512] Allow EVEX encoding unordered/ordered/equal/notequal VCMPPS/PD/SS/SD to...
Craig Topper [Sat, 27 Aug 2016 05:22:15 +0000 (05:22 +0000)]
[AVX-512] Allow EVEX encoding unordered/ordered/equal/notequal VCMPPS/PD/SS/SD to be commuted just like the SSE and AVX counterparts.

llvm-svn: 279914

5 years ago[X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted.
Craig Topper [Sat, 27 Aug 2016 05:22:12 +0000 (05:22 +0000)]
[X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted.

llvm-svn: 279913

5 years ago[AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd.
Craig Topper [Sat, 27 Aug 2016 05:22:08 +0000 (05:22 +0000)]
[AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd.

llvm-svn: 279912

5 years ago[LTO] Don't create a new common unless merged has different size
Teresa Johnson [Sat, 27 Aug 2016 04:41:22 +0000 (04:41 +0000)]
[LTO] Don't create a new common unless merged has different size

This addresses a regression in common handling from the new LTO
API in r278338. Only create a new common if the size is different.
The type comparison against an array type fails when the size is
different but not an array. GlobalMerge does not handle the
array types as well and we lose some global merging opportunities.

Reviewers: mehdi_amini

Subscribers: junbuml, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D23955

llvm-svn: 279911

5 years agoAMDGPU: Mark sched model complete
Matt Arsenault [Sat, 27 Aug 2016 03:39:27 +0000 (03:39 +0000)]
AMDGPU: Mark sched model complete

Fixes bug 26800

llvm-svn: 279910

5 years agoAMDGPU: Remove unneeded implicit exec uses/defs
Matt Arsenault [Sat, 27 Aug 2016 03:00:51 +0000 (03:00 +0000)]
AMDGPU: Remove unneeded implicit exec uses/defs

SI_BREAK, SI_IF_BREAK, and SI_ELSE_BREAK do not def exec.
SI_IF_BREAK and SI_ELSE_BREAK do not read it either.

llvm-svn: 279909

5 years ago[Orc] Explicitly specify type for assignment.
Lang Hames [Sat, 27 Aug 2016 02:59:24 +0000 (02:59 +0000)]
[Orc] Explicitly specify type for assignment.

This should fix the MSVC errors in

llvm-svn: 279908

5 years agoGVN-hoist: invalidate MD cache (PR29144)
Sebastian Pop [Sat, 27 Aug 2016 02:48:41 +0000 (02:48 +0000)]
GVN-hoist: invalidate MD cache (PR29144)

Without invalidating the entries in the MD cache we would try to access instructions
that were removed in previous iterations of hoisting.

Differential Revision: https://reviews.llvm.org/D23927

llvm-svn: 279907

5 years ago[RegBankSelect] Do not abort when the target wants to fall back.
Quentin Colombet [Sat, 27 Aug 2016 02:38:27 +0000 (02:38 +0000)]
[RegBankSelect] Do not abort when the target wants to fall back.

llvm-svn: 279906

5 years ago[InstructionSelect] Do not abort when the target wants to fall back.
Quentin Colombet [Sat, 27 Aug 2016 02:38:24 +0000 (02:38 +0000)]
[InstructionSelect] Do not abort when the target wants to fall back.

llvm-svn: 279905

5 years ago[MachineLegalize] Do not abort when the target wants to fall back.
Quentin Colombet [Sat, 27 Aug 2016 02:38:21 +0000 (02:38 +0000)]
[MachineLegalize] Do not abort when the target wants to fall back.

llvm-svn: 279904

5 years agoAdd attribute noreturn to functions that throw
Aditya Kumar [Sat, 27 Aug 2016 02:26:42 +0000 (02:26 +0000)]
Add attribute noreturn to functions that throw

Reviewers: mclow.lists, EricWF, howard.hinnant, sebpop
Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D21232

llvm-svn: 279903

5 years agoAMDGPU: Select mulhi 24-bit instructions
Matt Arsenault [Sat, 27 Aug 2016 01:32:27 +0000 (01:32 +0000)]
AMDGPU: Select mulhi 24-bit instructions

llvm-svn: 279902

5 years agoAMDGPU: Move cndmask pseudo to be isel pseudo
Matt Arsenault [Sat, 27 Aug 2016 01:00:37 +0000 (01:00 +0000)]
AMDGPU: Move cndmask pseudo to be isel pseudo

There's only one use of this for the convenience
of a pattern. I think v_mov_b64_pseudo should also be
moved, but SIFoldOperands does currently make use of it.

llvm-svn: 279901

5 years agoAMDGPU: Fix sched type for branches
Matt Arsenault [Sat, 27 Aug 2016 00:51:02 +0000 (00:51 +0000)]
AMDGPU: Fix sched type for branches

llvm-svn: 279900

5 years agoAMDGPU: Remove register operand from si_mask_branch
Matt Arsenault [Sat, 27 Aug 2016 00:42:21 +0000 (00:42 +0000)]
AMDGPU: Remove register operand from si_mask_branch

It isn't used for anything, and is also misleading since
it could be spilled at the end of the block, so it can't be relied
on. There ends up being a verifier error about using an undefined
register since the spill kills the register.

llvm-svn: 279899

5 years ago[asan] restrict release_to_os_test.cc to x86_64
Kostya Serebryany [Sat, 27 Aug 2016 00:36:20 +0000 (00:36 +0000)]
[asan] restrict release_to_os_test.cc to x86_64

llvm-svn: 279898

5 years agoThis test now succeeds.
Jim Ingham [Sat, 27 Aug 2016 00:35:48 +0000 (00:35 +0000)]
This test now succeeds.

llvm-svn: 279897

5 years agoFixed the location of a conditional to make the following code clearer.
Sean Callanan [Sat, 27 Aug 2016 00:35:37 +0000 (00:35 +0000)]
Fixed the location of a conditional to make the following code clearer.

llvm-svn: 279896

5 years agoAMDGPU: Improve error reporting for maximum branch distance
Matt Arsenault [Sat, 27 Aug 2016 00:21:22 +0000 (00:21 +0000)]
AMDGPU: Improve error reporting for maximum branch distance

Unfortunately this seems to only help the assembler diagnostic.

llvm-svn: 279895

5 years agoThe error stream in IRForTarget is never null, so use it instead of the log.
Sean Callanan [Sat, 27 Aug 2016 00:20:38 +0000 (00:20 +0000)]
The error stream in IRForTarget is never null, so use it instead of the log.

llvm-svn: 279894

5 years ago[CMake] Only generate Components.cmake if components are specified
Chris Bieneman [Sat, 27 Aug 2016 00:19:51 +0000 (00:19 +0000)]
[CMake] Only generate Components.cmake if components are specified

Generating the Components import file is useless if there are no components coming in from the runtimes configuration, so we should skip generation in that case.

This also should fix the configuration error that Renato reported on llvm-dev.

llvm-svn: 279893

5 years ago[ORC] Fix typo in LogicalDylib, add unit test.
Lang Hames [Sat, 27 Aug 2016 00:19:05 +0000 (00:19 +0000)]
[ORC] Fix typo in LogicalDylib, add unit test.

llvm-svn: 279892

5 years ago[GlobalISel] Add a fallback path to SDISel.
Quentin Colombet [Sat, 27 Aug 2016 00:18:31 +0000 (00:18 +0000)]
[GlobalISel] Add a fallback path to SDISel.

When global-isel fails on a MachineFunction MF, MF will be cleaned up
and given to SDISel.
Thanks to this fallback, we can already perform correctness test even if
we support only a small portion of the functions in a test.

llvm-svn: 279891

5 years ago[AArch64][CallLowering] Do not assert for not implemented part.
Quentin Colombet [Sat, 27 Aug 2016 00:18:28 +0000 (00:18 +0000)]
[AArch64][CallLowering] Do not assert for not implemented part.

When doing the ABI lowering, report a failure to the caller instead of
asserting. This gives a chance for the caller to recover.

llvm-svn: 279890

5 years ago[GlobalISel] Teach the core pipeline not to run if ISel failed.
Quentin Colombet [Sat, 27 Aug 2016 00:18:24 +0000 (00:18 +0000)]
[GlobalISel] Teach the core pipeline not to run if ISel failed.

llvm-svn: 279889

5 years ago[X86] Add baseline test for "odd" shuffles. NFC.
Michael Kuperstein [Sat, 27 Aug 2016 00:10:24 +0000 (00:10 +0000)]
[X86] Add baseline test for "odd" shuffles. NFC.

Adds a baseline test for lowering shuffles where the width of the output
vector is not twice the size of the input vectors. Many of those sequences
are suboptimal, and will hopefully be improved in follow-up patches.

llvm-svn: 279888

5 years ago[asan] first attempt at releasing free-d memory back to the system using madvise...
Kostya Serebryany [Fri, 26 Aug 2016 23:58:42 +0000 (23:58 +0000)]
[asan] first attempt at releasing free-d memory back to the system using madvise. Requires quite some tuning.

llvm-svn: 279887

5 years ago[IRTranslator] Do not abort when the target wants to fall back.
Quentin Colombet [Fri, 26 Aug 2016 23:49:05 +0000 (23:49 +0000)]
[IRTranslator] Do not abort when the target wants to fall back.

Every pass in the GlobalISel pipeline will need to do something similar.

llvm-svn: 279886

5 years ago[MFProperties] Introduce a FailedISel property.
Quentin Colombet [Fri, 26 Aug 2016 23:49:01 +0000 (23:49 +0000)]
[MFProperties] Introduce a FailedISel property.

This is used to communicate that the instruction selection pipeline
failed at some point.
Another way to achieve that would be to have some kind of conditional
scheduling in the PassManager, such that we only schedule a pass based
on the success/failure of another one. The property approach has the
advantage of being lightweight and solve the problem at stake.

llvm-svn: 279885

5 years agoFixed a bad lldbassert() condition.
Sean Callanan [Fri, 26 Aug 2016 23:48:03 +0000 (23:48 +0000)]
Fixed a bad lldbassert() condition.

llvm-svn: 279884

5 years ago[ThinLTO] Move loading of cache entry to client
Teresa Johnson [Fri, 26 Aug 2016 23:29:14 +0000 (23:29 +0000)]
[ThinLTO] Move loading of cache entry to client

Have the cache pass back the path to the cache entry when it
is ready to be loaded, instead of a buffer.

For gold-plugin we can simply pass this file back to gold directly,
which avoids expensive writing of a separate tmp file. Ensure
the cache entry is not deleted on cleanup by adjusting the setting
of the IsTemporary flags.

Moved the loading of the buffer into llvm-lto2 to maintain current

Reviewers: mehdi_amini

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D23946

llvm-svn: 279883

5 years agoTables of command options in LLDB benefit from hand-formatting to make it
Kate Stone [Fri, 26 Aug 2016 23:28:47 +0000 (23:28 +0000)]
Tables of command options in LLDB benefit from hand-formatting to make it
easier to scan a set of options with a relatively large number of positional
arguments. This commit standardizes their formatting throughout LLDB and
applies surrounding directives to exempt them from being formatted by

These kinds of exemptions should be rare cases that benefit significantly
from alternative formatting. They also imply a long-term obligation to
maintain their format since the automated tools will not do so.

llvm-svn: 279882

5 years agoAdding document describing the use of the -opt-bisect-limit option.
Andrew Kaylor [Fri, 26 Aug 2016 23:11:48 +0000 (23:11 +0000)]
Adding document describing the use of the -opt-bisect-limit option.

llvm-svn: 279881

5 years ago[asan] Mark symbolize_pc.cc as UNSUPPORTED on i386-apple.
Akira Hatanaka [Fri, 26 Aug 2016 23:08:28 +0000 (23:08 +0000)]
[asan] Mark symbolize_pc.cc as UNSUPPORTED on i386-apple.

atos currently doesn't work well when loaded from 32-bit binaries, which
was causing some of the bots to fail. Disable this test until we can
come up with a better fix.

llvm-svn: 279880

5 years ago[TargetPassConfig] Add a target hook to know what GlobalISel should do on error.
Quentin Colombet [Fri, 26 Aug 2016 22:32:59 +0000 (22:32 +0000)]
[TargetPassConfig] Add a target hook to know what GlobalISel should do on error.

By default, this hook tells GlobalISel to abort (report a fatal error)
when it encounters an error. The alternative will be to fall back on
This fall back will be removed when the bring-up of GlobalISel is over.

llvm-svn: 279879

5 years ago[IRTranslator][NFC] Use DEBUG_TYPE instead of repeating the name.
Quentin Colombet [Fri, 26 Aug 2016 22:32:57 +0000 (22:32 +0000)]
[IRTranslator][NFC] Use DEBUG_TYPE instead of repeating the name.

llvm-svn: 279878

5 years ago[SelectionDAG] Do not run the ISel process on already selected code.
Quentin Colombet [Fri, 26 Aug 2016 22:32:55 +0000 (22:32 +0000)]
[SelectionDAG] Do not run the ISel process on already selected code.

Right now, this cannot happen, but with the fall back path of GlobalISel
it will show up eventually.

llvm-svn: 279877

5 years ago[MachineFunction] Introduce a reset method.
Quentin Colombet [Fri, 26 Aug 2016 22:32:53 +0000 (22:32 +0000)]
[MachineFunction] Introduce a reset method.

This method allows to reset the state of a MachineFunction as if it was
just created. This will be used during the bring-up of GlobalISel to
provide a way to fallback on SelectionDAG. That way, we can start doing
correctness testing even if we are not able to select all functions via
the global instruction selector.

llvm-svn: 279876