lldb.git
4 years agoFixed build failure for revision r310261
Abhishek Aggarwal [Mon, 7 Aug 2017 17:15:26 +0000 (17:15 +0000)]
Fixed build failure for revision r310261

 -- Was failing for Linux

llvm-svn: 310270

4 years agoAMDGPU: Use a custom areInlineCompatible
Matt Arsenault [Mon, 7 Aug 2017 17:08:44 +0000 (17:08 +0000)]
AMDGPU: Use a custom areInlineCompatible

Fixes not inlining OpenCL library functions on AMDGPU,
which don't have an explicitly set target-cpu.

llvm-svn: 310269

4 years ago[X86][AVX] Add full test coverage of subvector_broadcasts from registers
Simon Pilgrim [Mon, 7 Aug 2017 16:49:09 +0000 (16:49 +0000)]
[X86][AVX] Add full test coverage of subvector_broadcasts from registers

X86SubVBroadcast is for memory subvector broadcasts, but we must test that it handles all cases without the load as well just in case.

This was noticed while I was triaging the test cases from PR34041.

llvm-svn: 310268

4 years ago[DebugInfo][DWARF] Address paulr's comment on rL310253.
Simon Dardis [Mon, 7 Aug 2017 16:08:11 +0000 (16:08 +0000)]
[DebugInfo][DWARF] Address paulr's comment on rL310253.

llvm-svn: 310267

4 years agoFixed build failure for revision r310261
Abhishek Aggarwal [Mon, 7 Aug 2017 15:53:30 +0000 (15:53 +0000)]
Fixed build failure for revision r310261

 -- Build was failing for freebsd

llvm-svn: 310266

4 years ago[X86][AVX] Cleanup subvector broadcast tests - remove old prefixes.
Simon Pilgrim [Mon, 7 Aug 2017 15:50:43 +0000 (15:50 +0000)]
[X86][AVX] Cleanup subvector broadcast tests - remove old prefixes.

llvm-svn: 310265

4 years ago[x86] revert r310208 to investigate test-suite failures (PR34105 / PR34097)
Sanjay Patel [Mon, 7 Aug 2017 15:47:48 +0000 (15:47 +0000)]
[x86] revert r310208 to investigate test-suite failures (PR34105 / PR34097)

llvm-svn: 310264

4 years ago[OpenMP] Add flag for specifying the target device architecture for OpenMP device...
Gheorghe-Teodor Bercea [Mon, 7 Aug 2017 15:39:11 +0000 (15:39 +0000)]
[OpenMP] Add flag for specifying the target device architecture for OpenMP device offloading

Summary:
OpenMP has the ability to offload target regions to devices which may have different architectures.

A new -fopenmp-target-arch flag is introduced to specify the device architecture.

In this patch I use the new flag to specify the compute capability of the underlying NVIDIA architecture for the OpenMP offloading CUDA tool chain.

Only a host-offloading test is provided since full device offloading capability will only be available when [[ https://reviews.llvm.org/D29654 | D29654 ]] lands.

Reviewers: hfinkel, Hahnfeld, carlo.bertolli, caomhin, ABataev

Reviewed By: hfinkel

Subscribers: guansong, cfe-commits

Tags: #openmp

Differential Revision: https://reviews.llvm.org/D34784

llvm-svn: 310263

4 years ago[DebugInfo][DWARF] Correct some usages of PRIx32 to PRIx64
Simon Dardis [Mon, 7 Aug 2017 15:37:57 +0000 (15:37 +0000)]
[DebugInfo][DWARF] Correct some usages of PRIx32 to PRIx64

These lead to tests failing spuriously as the values after being rendered to a
string were incorrect.

Reviewers: clayborg

Differential Revision: https://reviews.llvm.org/D36319

llvm-svn: 310262

4 years agoTool for using Intel(R) Processor Trace hardware feature
Abhishek Aggarwal [Mon, 7 Aug 2017 15:26:11 +0000 (15:26 +0000)]
Tool for using Intel(R) Processor Trace hardware feature

Summary:
1. Provide single library for all Intel specific hardware features instead
    of individual libraries for each feature
2. Added Intel(R) Processor Trace hardware feature in this single library.
    Details about the tool implementing this feature is as follows:

     Tool developed on top of LLDB to provide its users the execution
     trace of the debugged inferiors. Tool's API are exposed as C++ object
     oriented interface in a shared library. API are designed especially to be
     easily integrable with IDEs providing LLDB as an application debugger.
     Entire API is also available as Python functions through a script bridging
     interface allowing development of python modules.

     This patch also provides a CLI wrapper to use the Tool through LLDB's command
     line. Highlights of the Tool and the wrapper are given below:

  ******************************
  Intel(R) Processor Trace Tool:
  ******************************
       - Provides execution trace of the debugged application
       - Uses Intel(R) Processor Trace hardware feature (already implemented inside LLDB)
         for this purpose
           -- Collects trace packets generated by this feature from LLDB, decodes and
              post-processes them
           -- Constructs the execution trace of the application
           -- Presents execution trace as a list of assembly instructions
       - Provides 4 APIs (exposed as C++ object oriented interface)
           -- start trace with configuration options for a thread/process,
           -- stop trace for a thread/process,
           -- get the execution flow (assembly instructions) for a thread,
           -- get trace specific information for a thread
       - Easily integrable into IDEs providing LLDB as application debugger
       - Entire API available as Python functions through script bridging interface
           -- Allows developing python apps on top of Tool
       - README_TOOL.txt provides more details about the Tool, its dependencies, building
         steps and API usage
       - Tool ready to use through LLDB's command line
           -- CLI wrapper has been developed on top of the Tool for this purpose

  *********************************
  CLI wrapper: cli-wrapper-pt.cpp
  *********************************
       - Provides 4 commands (syntax similar to LLDB's CLI commands):
           -- processor-trace start
           -- processor-trace stop
           -- processor-trace show-trace-options
           -- processor-trace show-instr-log
       - README_CLI.txt provides more details about commands and their options

Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com>
Reviewers: clayborg, jingham, lldb-commits, labath

Reviewed By: clayborg

Subscribers: ravitheja, emaste, krytarowski, mgorny

Differential Revision: https://reviews.llvm.org/D33035

llvm-svn: 310261

4 years ago[SLP] General improvements of SLP vectorization process.
Alexey Bataev [Mon, 7 Aug 2017 15:25:49 +0000 (15:25 +0000)]
[SLP] General improvements of SLP vectorization process.

Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:

1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the
array. This array is processed only after the vectorization of the
first-after-these instructions key node is finished. Vectorization goes
in reverse order to try to vectorize as much code as possible.

Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon

Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits

Differential Revision: https://reviews.llvm.org/D29826

llvm-svn: 310260

4 years agoFix typo in comment
Matt Arsenault [Mon, 7 Aug 2017 14:58:43 +0000 (14:58 +0000)]
Fix typo in comment

llvm-svn: 310259

4 years agoAMDGPU: Cleanup subtarget features
Matt Arsenault [Mon, 7 Aug 2017 14:58:04 +0000 (14:58 +0000)]
AMDGPU: Cleanup subtarget features

Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.

Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.

llvm-svn: 310258

4 years agoRevert "[SLP] General improvements of SLP vectorization process."
Alexey Bataev [Mon, 7 Aug 2017 14:51:52 +0000 (14:51 +0000)]
Revert "[SLP] General improvements of SLP vectorization process."

This reverts commit r310255.

llvm-svn: 310257

4 years ago[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.
Nirav Dave [Mon, 7 Aug 2017 14:07:49 +0000 (14:07 +0000)]
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.

Relanding after case to insert explicit truncation as necessary.

Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.

Reviewers: efriedma, RKSimon, spatel

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D35566

llvm-svn: 310256

4 years ago[SLP] General improvements of SLP vectorization process.
Alexey Bataev [Mon, 7 Aug 2017 14:03:17 +0000 (14:03 +0000)]
[SLP] General improvements of SLP vectorization process.

Summary:
Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:
1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the array. This array is processed only after the vectorization of the first-after-these instructions key node is finished. Vectorization goes in reverse order to try to vectorize as much code as possible.

Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon

Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits

Differential Revision: https://reviews.llvm.org/D29826

llvm-svn: 310255

4 years ago[TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true
Nirav Dave [Mon, 7 Aug 2017 13:55:27 +0000 (13:55 +0000)]
[TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true

Relanding after fixing UB issue with DefaultOffsets.

Consider the following instruction: "inst.eq $dst, $src" where ".eq"
is an optional flag operand.  The $src and $dst operands are
registers.  If we parse the instruction "inst r0, r1", the flag is not
present and it will be marked in the "OptionalOperandsMask" variable.
After the matching is complete we call the "convertToMCInst" method.

The current implementation works only if the optional operands are at
the end of the array.  The "Operands" array looks like [token:"inst",
reg:r0, reg:r1].  The first operand that must be added to the MCInst
is the destination, the r0 register.  The "OpIdx" (in the Operands
array) for this register is 2.  However, since the flag is not present
in the Operands, the actual index for r0 should be 1.  The flag is not
present since we rely on the default value.

This patch removes the "NumDefaults" variable and replaces it with an
array (DefaultsOffset).  This array contains an index for each operand
(excluding the mnemonic).  At each index, the array contains the
number of optional operands that should be subtracted.  For the
previous example, this array looks like this: [0, 1, 1].  When we need
to access the r0 register, we compute its index as 2 -
DefaultsOffset[1] = 1.

Patch by Alexandru Guduleasa!

Reviewers: SamWot, nhaustov, niravd

Reviewed By: niravd

Subscribers: vitalybuka, llvm-commits

Differential Revision: https://reviews.llvm.org/D35998

llvm-svn: 310254

4 years ago[DebugInfo][DWARF] Use PRIx64 explicitly in output.
Simon Dardis [Mon, 7 Aug 2017 13:30:03 +0000 (13:30 +0000)]
[DebugInfo][DWARF] Use PRIx64 explicitly in output.

llvm-svn: 310253

4 years ago[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF16...
Michael Zuckerman [Mon, 7 Aug 2017 13:22:39 +0000 (13:22 +0000)]
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF16 stride 4).

This patch expands the support of lowerInterleavedStore to 16x8i stride 4.

LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=16) and we plan to include more patterns in the future.

The patch goal is to optimize the following sequence:
At the end of the computation, we have ymm2, ymm0, ymm12 and ymm3 holding
each 16 chars:

c0, c1, , c16
m0, m1, , m16
y0, y1, , y16
k0, k1, ., k16

And these need to be transposed/interleaved and stored like so:

c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....

Differential Revision: https://reviews.llvm.org/D35829

llvm-svn: 310252

4 years ago[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
Dmitry Preobrazhensky [Mon, 7 Aug 2017 13:14:12 +0000 (13:14 +0000)]
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI

See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621

Reviewers: vpykhtin, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D35902

llvm-svn: 310251

4 years ago[llvm-objdump] Use PRIx64 for output of ARM64_RELOC_ADDEND
Simon Dardis [Mon, 7 Aug 2017 12:29:38 +0000 (12:29 +0000)]
[llvm-objdump] Use PRIx64 for output of ARM64_RELOC_ADDEND

llvm-svn: 310250

4 years ago[X86][AVX] Added test for broadcast shuffle with undefs (PR34041)
Simon Pilgrim [Mon, 7 Aug 2017 12:24:33 +0000 (12:24 +0000)]
[X86][AVX] Added test for broadcast shuffle with undefs (PR34041)

llvm-svn: 310249

4 years agoAdd NetBSD support in sanitizer_test_utils.h
Kamil Rytarowski [Mon, 7 Aug 2017 10:59:44 +0000 (10:59 +0000)]
Add NetBSD support in sanitizer_test_utils.h

Summary:
NetBSD ships with printf_l(3) like FreeBSD.

NetBSD does not ship with memalign, pvalloc, malloc with "usable size"
and is the same here as Darwin, Android, FreeBSD and Windows.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, vitalybuka, kcc, fjricci, filcab

Reviewed By: vitalybuka

Subscribers: srhines, llvm-commits, emaste, kubamracek, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36373

llvm-svn: 310248

4 years agoAdd NetBSD support in asan_errors.cc
Kamil Rytarowski [Mon, 7 Aug 2017 10:58:48 +0000 (10:58 +0000)]
Add NetBSD support in asan_errors.cc

Summary:
Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, fjricci, vitalybuka, filcab, kcc

Reviewed By: vitalybuka

Subscribers: llvm-commits, kubamracek, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36374

llvm-svn: 310247

4 years agoAdd NetBSD support in asan_interceptors.h
Kamil Rytarowski [Mon, 7 Aug 2017 10:57:58 +0000 (10:57 +0000)]
Add NetBSD support in asan_interceptors.h

Summary:
Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, filcab, kcc, fjricci, vitalybuka

Reviewed By: vitalybuka

Subscribers: kubamracek, llvm-commits, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36375

llvm-svn: 310246

4 years agoEnable LLVM asan support for NetBSD/i386
Kamil Rytarowski [Mon, 7 Aug 2017 10:57:03 +0000 (10:57 +0000)]
Enable LLVM asan support for NetBSD/i386

Summary:
Verified to work and useful to run check-asan, as this target tests 32-bit and 64-bit execution.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, filcab, dim, vitalybuka

Reviewed By: vitalybuka

Subscribers: #sanitizers, cfe-commits

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36378

llvm-svn: 310245

4 years ago[asan] Return sizeof missed by r309914
Vitaly Buka [Mon, 7 Aug 2017 09:08:44 +0000 (09:08 +0000)]
[asan] Return sizeof missed by r309914

llvm-svn: 310244

4 years ago[ARM] Fix assembly and disassembly for VMRS/VMSR
Andre Vieira [Mon, 7 Aug 2017 08:41:05 +0000 (08:41 +0000)]
[ARM] Fix assembly and disassembly for VMRS/VMSR

This patch addresses two issues with assembly and disassembly for VMRS/VMSR:

1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
  accepted for non ARMv8-A targets.

2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only
   ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.

This patch addresses those issues and adds tests for these cases.

Differential Revision: https://reviews.llvm.org/D36306

llvm-svn: 310243

4 years ago[asan] Fix asan dynamic shadow check before copyArgsPassedByValToAllocas
Vitaly Buka [Mon, 7 Aug 2017 07:35:33 +0000 (07:35 +0000)]
[asan] Fix asan dynamic shadow check before copyArgsPassedByValToAllocas

llvm-svn: 310242

4 years ago[asan] Disable checking of arguments passed by value for --asan-force-dynamic-shadow
Vitaly Buka [Mon, 7 Aug 2017 07:12:34 +0000 (07:12 +0000)]
[asan] Disable checking of arguments passed by value for --asan-force-dynamic-shadow

Fails with "Instruction does not dominate all uses!"

llvm-svn: 310241

4 years agoAdd -asan-force-dynamic-shadow test
Vitaly Buka [Mon, 7 Aug 2017 07:12:33 +0000 (07:12 +0000)]
Add -asan-force-dynamic-shadow test

llvm-svn: 310240

4 years ago[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks
Guy Blank [Mon, 7 Aug 2017 05:51:14 +0000 (05:51 +0000)]
[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks

The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types.
But before calling CodeGenAndEmitDAG we build the DAG for the basic block.
So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'.

This patch sets the flag to false before SDAG building each basic block.

Differential Revision:
https://reviews.llvm.org/D33435

llvm-svn: 310239

4 years ago[Reassociate] Use a range loop for clarity. NFCI.
Davide Italiano [Mon, 7 Aug 2017 01:57:21 +0000 (01:57 +0000)]
[Reassociate] Use a range loop for clarity. NFCI.

While here, rename `i` to `Rank` as the latter is more
self-explanatory (and this code also uses `I` two lines below to
identify an Instruction).

llvm-svn: 310238

4 years ago[Reassociate] Try to bail out early when canonicalizing.
Davide Italiano [Mon, 7 Aug 2017 01:49:09 +0000 (01:49 +0000)]
[Reassociate] Try to bail out early when canonicalizing.

This commit rearranges the checks to avoid calls to getRank()
when not needed (e.g. when RHS == LHS).

llvm-svn: 310237

4 years ago[ScopInfo] Make Scop::canAlwaysBeHoisted a member function
Tobias Grosser [Mon, 7 Aug 2017 00:10:11 +0000 (00:10 +0000)]
[ScopInfo] Make Scop::canAlwaysBeHoisted a member function

llvm-svn: 310236

4 years ago[ScopInfo] Move Scop::addInvariantLoads to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 23:50:25 +0000 (23:50 +0000)]
[ScopInfo] Move Scop::addInvariantLoads to isl++ [NFC]

llvm-svn: 310235

4 years ago[InstCombine] Remove shift handling from OptAndOp.
Craig Topper [Sun, 6 Aug 2017 23:30:49 +0000 (23:30 +0000)]
[InstCombine] Remove shift handling from OptAndOp.

Summary: This is all handled by SimplifyDemandedBits.

Reviewers: spatel, davide

Reviewed By: davide

Subscribers: davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D36382

llvm-svn: 310234

4 years ago[InstCombine] Support (X ^ C1) & C2 --> (X & C2) ^ (C1&C2) for vector splats.
Craig Topper [Sun, 6 Aug 2017 23:11:49 +0000 (23:11 +0000)]
[InstCombine] Support (X ^ C1) & C2 --> (X & C2) ^ (C1&C2) for vector splats.

llvm-svn: 310233

4 years ago[InstCombine] Support '(C - X) ^ signmask -> (C + signmask - X)' and '(X + C) ^ signm...
Craig Topper [Sun, 6 Aug 2017 22:17:21 +0000 (22:17 +0000)]
[InstCombine] Support '(C - X) ^ signmask -> (C + signmask - X)' and '(X + C) ^ signmask -> (X + C + signmask)' for vector splats.

llvm-svn: 310232

4 years ago[ScopInfo] Move Scop::getPwAffOnly to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 21:42:38 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getPwAffOnly to isl++ [NFC]

llvm-svn: 310231

4 years ago[ScopInfo] Move Scop::getDomains to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 21:42:25 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getDomains to isl++ [NFC]

llvm-svn: 310230

4 years ago[ScopInfo] Move Scop::getInvalidContext to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 21:42:16 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getInvalidContext to isl++ [NFC]

llvm-svn: 310229

4 years ago[ScopInfo] Move Scop::getAssumedContext to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 21:42:09 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getAssumedContext to isl++ [NFC]

llvm-svn: 310228

4 years ago[SLPVectorizer][X86] Cleanup test case. NFCI
Simon Pilgrim [Sun, 6 Aug 2017 20:50:19 +0000 (20:50 +0000)]
[SLPVectorizer][X86] Cleanup test case. NFCI

Remove excess attributes/metadata

llvm-svn: 310227

4 years ago[demangler] Fix another oss-fuzz bug
Erik Pilkington [Sun, 6 Aug 2017 20:46:33 +0000 (20:46 +0000)]
[demangler] Fix another oss-fuzz bug

llvm-svn: 310226

4 years ago[ScopInfo] Move Scop::addNonEmptyDomainConstraints to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 20:19:26 +0000 (20:19 +0000)]
[ScopInfo] Move Scop::addNonEmptyDomainConstraints to isl++ [NFC]

llvm-svn: 310225

4 years ago[ScopInfo] Translate Scop::getParamSpace to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 20:11:59 +0000 (20:11 +0000)]
[ScopInfo] Translate Scop::getParamSpace to isl++ [NFC]

llvm-svn: 310224

4 years ago[llvm-dlltool] Map the "arm64" machine type
Martin Storsjo [Sun, 6 Aug 2017 19:58:13 +0000 (19:58 +0000)]
[llvm-dlltool] Map the "arm64" machine type

Differential Revision: https://reviews.llvm.org/D36365

llvm-svn: 310223

4 years ago[test] Remove an unintentional -x cl flag in an aarch64-windows test
Martin Storsjo [Sun, 6 Aug 2017 19:57:49 +0000 (19:57 +0000)]
[test] Remove an unintentional -x cl flag in an aarch64-windows test

This test was only intended to test compiling C, not OpenCL.

Differential Revision: https://reviews.llvm.org/D36363

llvm-svn: 310222

4 years ago[ScopInfo] Translate Scop::getContext to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 19:52:38 +0000 (19:52 +0000)]
[ScopInfo] Translate Scop::getContext to isl++ [NFC]

llvm-svn: 310221

4 years ago[ScopInfo] Translate Scop::getIdForParam to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 19:31:27 +0000 (19:31 +0000)]
[ScopInfo] Translate Scop::getIdForParam to isl++ [NFC]

llvm-svn: 310220

4 years ago[ScopInfo] Move get*Writes/getReads/getAccesses to isl++
Tobias Grosser [Sun, 6 Aug 2017 19:22:27 +0000 (19:22 +0000)]
[ScopInfo] Move get*Writes/getReads/getAccesses to isl++

llvm-svn: 310219

4 years agoRemove functional changes that sneaked in by accident in r308892
Tobias Grosser [Sun, 6 Aug 2017 18:59:19 +0000 (18:59 +0000)]
Remove functional changes that sneaked in by accident in r308892

llvm-svn: 310218

4 years agoAMDGPU: Fix typo in feature description
Matt Arsenault [Sun, 6 Aug 2017 18:13:23 +0000 (18:13 +0000)]
AMDGPU: Fix typo in feature description

llvm-svn: 310217

4 years ago[ScopInfo] Move ScopStmt::setAstBuild/getAstBuild to isl++
Tobias Grosser [Sun, 6 Aug 2017 17:53:04 +0000 (17:53 +0000)]
[ScopInfo] Move ScopStmt::setAstBuild/getAstBuild to isl++

llvm-svn: 310216

4 years ago[ScopInfo] Move ScopStmt::getSchedule to isl++
Tobias Grosser [Sun, 6 Aug 2017 17:45:28 +0000 (17:45 +0000)]
[ScopInfo] Move ScopStmt::getSchedule to isl++

llvm-svn: 310215

4 years ago[ScopInfo] Move getPredecessorDomainConstraints to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 17:31:38 +0000 (17:31 +0000)]
[ScopInfo] Move getPredecessorDomainConstraints to isl++ [NFC]

llvm-svn: 310214

4 years ago[ScopInfo] Move InvariantAccess to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 17:25:14 +0000 (17:25 +0000)]
[ScopInfo] Move InvariantAccess to isl++ [NFC]

llvm-svn: 310213

4 years ago[ScopInfo] Update comments to refer to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 17:25:09 +0000 (17:25 +0000)]
[ScopInfo] Update comments to refer to isl++ [NFC]

llvm-svn: 310212

4 years ago[ScopInfo] Move ScopArrayInfo::ScopArrayInfo to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 17:25:05 +0000 (17:25 +0000)]
[ScopInfo] Move ScopArrayInfo::ScopArrayInfo to isl++ [NFC]

llvm-svn: 310211

4 years ago[ScopInfo] Move ScopStmt::ScopStmt to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 17:24:59 +0000 (17:24 +0000)]
[ScopInfo] Move ScopStmt::ScopStmt to isl++ [NFC]

llvm-svn: 310210

4 years agoMove ScopInfo::getDomain(), getDomainSpace(), getDomainId() to isl++
Tobias Grosser [Sun, 6 Aug 2017 16:39:52 +0000 (16:39 +0000)]
Move ScopInfo::getDomain(), getDomainSpace(), getDomainId() to isl++

llvm-svn: 310209

4 years ago[x86] use more shift or LEA for select-of-constants
Sanjay Patel [Sun, 6 Aug 2017 16:27:07 +0000 (16:27 +0000)]
[x86] use more shift or LEA for select-of-constants

We can convert any select-of-constants to math ops:
http://rise4fun.com/Alive/d7d

For this patch, I'm enhancing an existing x86 transform that uses fake multiplies
(they always become shl/lea) to avoid cmov or branching. The current code misses
cases where we have a negative constant and a positive constant, so this is just
trying to plug that hole.

The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start
with a select in IR, create a select DAG node, convert it into a sext, convert it
back into a select, and then lower it to sext machine code.

Some notes about the test diffs:

1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR.
2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. I
   think we could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on
   a different reg? That's a post-DAG problem though.
3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if
   that's a regression, but I think those would always be nearly equivalent.
4. pr22338.ll and sext-i1.ll - These tests have undef operands, so I don't think we actually care about these diffs.
5. sbb.ll - This shows a win for what I think is a common case: choose -1 or 0.
6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again.
7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops.

Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass.

Differential Revision: https://reviews.llvm.org/D35340

llvm-svn: 310208

4 years agoMove ScopStmt::Domain to isl++
Tobias Grosser [Sun, 6 Aug 2017 16:11:53 +0000 (16:11 +0000)]
Move ScopStmt::Domain to isl++

llvm-svn: 310207

4 years agoUpdate to a newer version of isl++
Tobias Grosser [Sun, 6 Aug 2017 15:56:45 +0000 (15:56 +0000)]
Update to a newer version of isl++

llvm-svn: 310206

4 years agoUpdate to isl-0.18-812-g565da6e
Tobias Grosser [Sun, 6 Aug 2017 15:51:16 +0000 (15:51 +0000)]
Update to isl-0.18-812-g565da6e

This update is mostly a maintenance update, but also exposes a couple of new
functions that will be needed for the next version of the isl++ bindings.

llvm-svn: 310205

4 years ago[Scopinfo] Fix memory corruption issue that sneaked into the previous commit
Tobias Grosser [Sun, 6 Aug 2017 15:47:04 +0000 (15:47 +0000)]
[Scopinfo] Fix memory corruption issue that sneaked into the previous commit

llvm-svn: 310204

4 years ago[ScopInfo] Move InvalidDomain to isl++ [NFC]
Tobias Grosser [Sun, 6 Aug 2017 15:36:48 +0000 (15:36 +0000)]
[ScopInfo] Move InvalidDomain to isl++ [NFC]

llvm-svn: 310203

4 years ago[X86] Add comment to match closing Defs = [FPSW]. NFCI.
Simon Pilgrim [Sun, 6 Aug 2017 13:21:09 +0000 (13:21 +0000)]
[X86] Add comment to match closing Defs = [FPSW]. NFCI.

llvm-svn: 310202

4 years ago[X86][X87] Regenerate inline-asm tests
Simon Pilgrim [Sun, 6 Aug 2017 12:17:10 +0000 (12:17 +0000)]
[X86][X87] Regenerate inline-asm tests

llvm-svn: 310201

4 years ago[AVR] Compute code model if one is not provided
Meador Inge [Sun, 6 Aug 2017 12:02:17 +0000 (12:02 +0000)]
[AVR] Compute code model if one is not provided

The patch from r310028 fixed things to work with the new
`LLVMTargetMachine` constructor that came in on r309911.
However, the fix was partial since an object of type
`CodeModel::Model` must be passed to `LLVMTargetMachine`
(not one of `Optional<CodeModel::Model>`).

This patch fixes the problem in the same fashion that r309911
did for other machines: by checking if the passed optional
code model has a value and using `CodeModel::Small` if not.

llvm-svn: 310200

4 years ago[Polly] Fix for the JSON Exporter
Tobias Grosser [Sun, 6 Aug 2017 11:41:10 +0000 (11:41 +0000)]
[Polly] Fix for the JSON Exporter

Summary:
Small patch to fix the JSON exporter.

Currently, using "opt -polly-export-jscop" does not generate jscop files, but gives an error:
*** Error in `opt': corrupted double-linked list: 0x0000000000bc4bb0 ***

Updated the function getAccessRelationStr() to work with the current version of getAccessRelation(), fixing the JSON exporter

Reviewers: bollu, grosser

Reviewed By: grosser

Subscribers: grosser, llvm-commits, pollydev

Tags: #polly

Differential Revision: https://reviews.llvm.org/D36370

llvm-svn: 310199

4 years ago[X86][X87] Add test case for PR34080
Simon Pilgrim [Sun, 6 Aug 2017 11:22:33 +0000 (11:22 +0000)]
[X86][X87] Add test case for PR34080

Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets.

pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations).

llvm-svn: 310198

4 years agoAdd missing 'REQUIRES: pollyacc' line
Tobias Grosser [Sun, 6 Aug 2017 11:21:09 +0000 (11:21 +0000)]
Add missing 'REQUIRES: pollyacc' line

llvm-svn: 310197

4 years ago[GPGPU] Make sure managed arrays are prepared at the beginning of the scop
Tobias Grosser [Sun, 6 Aug 2017 11:10:38 +0000 (11:10 +0000)]
[GPGPU] Make sure managed arrays are prepared at the beginning of the scop

Summary:
This resolves some "instruction does not dominate use" errors, as we used to
prepare the arrays at the location of the first kernel, which not necessarily
dominated all other kernel calls.

Reviewers: Meinersbur, bollu, singam-sanjay

Subscribers: nemanjai, pollydev, llvm-commits, kbarton

Differential Revision: https://reviews.llvm.org/D36372

llvm-svn: 310196

4 years ago[InstCombine] Support ~(c-X) --> X+(-c-1) and ~(X-c) --> (-c-1)-X for splat vectors.
Craig Topper [Sun, 6 Aug 2017 06:28:41 +0000 (06:28 +0000)]
[InstCombine] Support ~(c-X) --> X+(-c-1) and ~(X-c) --> (-c-1)-X for splat vectors.

llvm-svn: 310195

4 years ago[GPGPU] Rename all, not only the first libdevice function
Tobias Grosser [Sun, 6 Aug 2017 03:04:15 +0000 (03:04 +0000)]
[GPGPU] Rename all, not only the first libdevice function

llvm-svn: 310194

4 years ago[Polly] [PPCGCodeGeneration] Deal with loops outside the Scop correctly in PPCGCodeGe...
Siddharth Bhat [Sun, 6 Aug 2017 02:39:05 +0000 (02:39 +0000)]
[Polly] [PPCGCodeGeneration] Deal with loops outside the Scop correctly in PPCGCodeGeneration.

A Scop with a loop outside it is not handled currently by
PPCGCodeGeneration. The test case is such that the Scop has only one inner loop
that is detected. This currently breaks codegen.

The fix is to reuse the existing mechanism in `IslNodeBuilder` within
`GPUNodeBuilder.

Differential Revision: https://reviews.llvm.org/D36290

llvm-svn: 310193

4 years ago[IslNodeBuilder] [NFC] Refactor creation of loop induction variables of loops outside...
Siddharth Bhat [Sun, 6 Aug 2017 02:07:11 +0000 (02:07 +0000)]
[IslNodeBuilder] [NFC] Refactor creation of loop induction variables of loops outside scops.

 This logic is duplicated, so we refactor it into a separate function.
 This will be used in a later patch to teach PPCGCodeGen code generation
 for loops that are outside the scop.

 Differential Revision: https://reviews.llvm.org/D36310

llvm-svn: 310192

4 years ago[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang...
Craig Topper [Sat, 5 Aug 2017 23:35:54 +0000 (23:35 +0000)]
[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang part

Summary:
On older processors this instruction encoding is treated as a NOP.

MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.

This change also seems to also be consistent with gcc behavior.

Fixes PR34079

Reviewers: RKSimon, zvi

Reviewed By: RKSimon

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D36362

llvm-svn: 310191

4 years ago[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled
Craig Topper [Sat, 5 Aug 2017 23:34:44 +0000 (23:34 +0000)]
[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled

Summary:
On older processors this instruction encoding is treated as a NOP.

MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.

This change also seems to also be consistent with gcc behavior.

Fixes PR34079

Reviewers: RKSimon, zvi

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36361

llvm-svn: 310190

4 years ago[ADT] Add a much simpler loop to DenseMap::clear when the types are
Chandler Carruth [Sat, 5 Aug 2017 22:48:37 +0000 (22:48 +0000)]
[ADT] Add a much simpler loop to DenseMap::clear when the types are
POD-like and we can just splat the empty key across memory.

Sadly we can't optimize the normal loop well enough because we can't
turn the conditional store into an unconditional store according to the
memory model.

This loop actually showed up in a profile of code that was calling clear
as a serious source of time. =[

llvm-svn: 310189

4 years ago[InstCombine] Regenerate test28_sub test case in xor.ll that I forgot to commit after...
Craig Topper [Sat, 5 Aug 2017 22:44:38 +0000 (22:44 +0000)]
[InstCombine] Regenerate test28_sub test case in xor.ll that I forgot to commit after fixing a typo in r310186.

llvm-svn: 310188

4 years ago[Polly] Fix typo. NFC.
Tobias Grosser [Sat, 5 Aug 2017 20:03:13 +0000 (20:03 +0000)]
[Polly] Fix typo. NFC.

Reviewers: grosser, Meinersbur, bollu

Differential Revision: https://reviews.llvm.org/D36356

llvm-svn: 310187

4 years ago[InstCombine] Fold (C - X) ^ signmask -> (C + signmask - X).
Craig Topper [Sat, 5 Aug 2017 20:00:44 +0000 (20:00 +0000)]
[InstCombine] Fold (C - X) ^ signmask -> (C + signmask - X).

llvm-svn: 310186

4 years ago[InstCombine] Teach the code that pulls logical operators through constant shifts...
Craig Topper [Sat, 5 Aug 2017 20:00:42 +0000 (20:00 +0000)]
[InstCombine] Teach the code that pulls logical operators through constant shifts to handle vector splats too.

llvm-svn: 310185

4 years ago[InstCombine] Support vector splats in foldSelectICmpAnd.
Craig Topper [Sat, 5 Aug 2017 20:00:41 +0000 (20:00 +0000)]
[InstCombine] Support vector splats in foldSelectICmpAnd.

Unfortunately, it looks like there's some other missed optimizations in the generated code for some of these cases. I'll try to look at some of those next.

llvm-svn: 310184

4 years ago[SLPVectorizer] Add extra parameter to setInsertPointAfterBundle to handle different...
Dinar Temirbulatov [Sat, 5 Aug 2017 18:43:52 +0000 (18:43 +0000)]
[SLPVectorizer] Add extra parameter to setInsertPointAfterBundle to handle different opcodes, NFCI.

Differential Revision: https://reviews.llvm.org/D35769

llvm-svn: 310183

4 years agoAdd NetBSD support in sanitizer_errno.h
Kamil Rytarowski [Sat, 5 Aug 2017 18:10:51 +0000 (18:10 +0000)]
Add NetBSD support in sanitizer_errno.h

Summary:
NetBSD ships with __errno (value for __errno_location) like Android.

Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, vitalybuka, fjricci, kcc, filcab

Reviewed By: vitalybuka

Subscribers: llvm-commits, srhines, kubamracek, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36360

llvm-svn: 310182

4 years ago[InstCombine] refactor trunc(binop) transforms; NFCI
Sanjay Patel [Sat, 5 Aug 2017 15:19:18 +0000 (15:19 +0000)]
[InstCombine] refactor trunc(binop) transforms; NFCI

In addition to moving the shift transforms over, we may want to
detect too-wide rotate patterns here (PR34046).

llvm-svn: 310181

4 years ago[ARM] The ARM backend is MachineVerifier clean now.
Florian Hahn [Sat, 5 Aug 2017 15:14:06 +0000 (15:14 +0000)]
[ARM] The ARM backend is MachineVerifier clean now.

Summary: Thanks everyone involved in fixing the outstanding issues.

Reviewers: rovka, MatzeB, efriedma

Reviewed By: MatzeB

Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D36153

llvm-svn: 310180

4 years agoAdd NetBSD support in sanitizer_unwind_linux_libcdep.cc
Kamil Rytarowski [Sat, 5 Aug 2017 13:36:49 +0000 (13:36 +0000)]
Add NetBSD support in sanitizer_unwind_linux_libcdep.cc

Summary:
NetBSD is a POSIX-like and BSD-family system.

Reuse FreeBSD and Linux code.

NetBSD uses DWARF ExceptionHandler.

Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, kcc, filcab, vitalybuka

Reviewed By: vitalybuka

Subscribers: srhines, emaste, llvm-commits, kubamracek, aprantl, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36314

llvm-svn: 310179

4 years ago[ARM] Add registers to debuginfo MIR test cases.
Florian Hahn [Sat, 5 Aug 2017 12:13:13 +0000 (12:13 +0000)]
[ARM] Add registers to debuginfo MIR test cases.

Summary:
MIRParserImpl::computeFunctionProperties uses MRI.getNumVirtRegs() to
set the NoVReg property. By adding a bunch of registers to the MIR test
cases, the NoVReg property is not set when importing the MIR. Otherwise
NoVReg is set after instruction selection while the machine instructions
still contain virtual registers, causing expensive checks to fail.

Reviewers: efriedma, MatzeB, aprantl

Reviewed By: MatzeB, aprantl

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D36152

llvm-svn: 310178

4 years agoAdd forgotten CMakeLists.txt file in unit-test
Tobias Grosser [Sat, 5 Aug 2017 09:44:11 +0000 (09:44 +0000)]
Add forgotten CMakeLists.txt file in unit-test

llvm-svn: 310177

4 years agoFix spelling error in previous commit
Tobias Grosser [Sat, 5 Aug 2017 09:39:00 +0000 (09:39 +0000)]
Fix spelling error in previous commit

llvm-svn: 310176

4 years ago[unittests] Add unittest for getPartialTilePrefixes
Tobias Grosser [Sat, 5 Aug 2017 09:38:09 +0000 (09:38 +0000)]
[unittests] Add unittest for getPartialTilePrefixes

In https://reviews.llvm.org/D36278 it was pointed out that the behavior of
getPartialTilePrefixes is not very well understood. To allow for a better
understanding, we first provide some basic unittests.

llvm-svn: 310175

4 years ago[LCG] Remove yet another variable only used inside of asserts.
Chandler Carruth [Sat, 5 Aug 2017 08:33:16 +0000 (08:33 +0000)]
[LCG] Remove yet another variable only used inside of asserts.

llvm-svn: 310174

4 years ago[LCG] Fold otherwise unused variable into assert.
Benjamin Kramer [Sat, 5 Aug 2017 08:28:48 +0000 (08:28 +0000)]
[LCG] Fold otherwise unused variable into assert.

No functionality change intended.

llvm-svn: 310173

4 years agoIPRA: Don't crash on null getCallPreservedMask
Matt Arsenault [Sat, 5 Aug 2017 07:50:18 +0000 (07:50 +0000)]
IPRA: Don't crash on null getCallPreservedMask

Kernels aren't callable, so they don't have a call preserved mask.

llvm-svn: 310172

4 years ago[LCG] Completely remove the parent set and leaf tracking for RefSCCs.
Chandler Carruth [Sat, 5 Aug 2017 07:37:00 +0000 (07:37 +0000)]
[LCG] Completely remove the parent set and leaf tracking for RefSCCs.

After the previous series of patches, this is now trivial and deletes
a pretty astonishing amount of complexity. This has been a long time
coming, as the move toward a PO sequence of RefSCCs started eroding the
underlying use cases for this half of the data structure.

Among the biggest advantages here is that now there aren't two
independent data structures that need to stay in sync.

Some of my profiling has also indicated that updating the parent sets
was among the most expensive parts of the lazy call graph. Eliminating
it whole sale is likely to be a nice win in terms of compile time.

Last but not least, I had discussed with some folks previously keeping
it around for asserts and other correctness checking, but once the
fundamentals of the parent and child checking were implemented without
the parent sets their value in correctness checking was tiny and no
where near worth the cost of the complexity required to keep everything
up-to-date.

llvm-svn: 310171