drivers/storage/atapi/atapi.h

   1 //
   2 //  ATAPI.H - defines and typedefs for the IDE Driver module.
   3 //
   4
   5 #ifndef __ATAPI_H
   6 #define __ATAPI_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #define  IDE_MAXIMUM_DEVICES    8
  13
  14 #define IDE_MAX_NAME_LENGTH     50
  15
  16 #define  IDE_SECTOR_BUF_SZ         512
  17 #define  IDE_MAX_SECTORS_PER_XFER  256
  18 #define  IDE_MAX_RESET_RETRIES     10000
  19 #define  IDE_MAX_POLL_RETRIES      100000
  20 #define  IDE_MAX_WRITE_RETRIES     1000
  21 #define  IDE_MAX_BUSY_RETRIES      50000
  22 #define  IDE_MAX_DRQ_RETRIES       10000
  23 //#define  IDE_MAX_CMD_RETRIES       1
  24 #define  IDE_MAX_CMD_RETRIES       0
  25 #define  IDE_CMD_TIMEOUT           5
  26 #define  IDE_RESET_PULSE_LENGTH    500  /* maybe a little too long */
  27 #define  IDE_RESET_BUSY_TIMEOUT    120
  28 #define  IDE_RESET_DRDY_TIMEOUT    120
  29
  30 // Control Block offsets and masks
  31 #define  IDE_REG_ALT_STATUS     0x0000
  32 #define  IDE_REG_DEV_CNTRL      0x0000  /* device control register */
  33 #define    IDE_DC_SRST            0x04  /* drive reset (both drives) */
  34 #define    IDE_DC_nIEN            0x02  /* IRQ enable (active low) */
  35 #define  IDE_REG_DRV_ADDR       0x0001
  36
  37 // Command Block offsets and masks
  38 #define  IDE_REG_DATA_PORT      0x0000
  39 #define  IDE_REG_ERROR          0x0001  /* error register */
  40 #define    IDE_ER_AMNF            0x01  /* addr mark not found */
  41 #define    IDE_ER_TK0NF           0x02  /* track 0 not found */
  42 #define    IDE_ER_ABRT            0x04  /* command aborted */
  43 #define    IDE_ER_MCR             0x08  /* media change requested */
  44 #define    IDE_ER_IDNF            0x10  /* ID not found */
  45 #define    IDE_ER_MC              0x20  /* Media changed */
  46 #define    IDE_ER_UNC             0x40  /* Uncorrectable data error */
  47 #define  IDE_REG_PRECOMP        0x0001
  48 #define  IDE_REG_SECTOR_CNT     0x0002
  49 #define  IDE_REG_SECTOR_NUM     0x0003
  50 #define  IDE_REG_CYL_LOW        0x0004
  51 #define  IDE_REG_CYL_HIGH       0x0005
  52 #define  IDE_REG_DRV_HEAD       0x0006
  53 #define    IDE_DH_FIXED           0xA0
  54 #define    IDE_DH_LBA             0x40
  55 #define    IDE_DH_HDMASK          0x0F
  56 #define    IDE_DH_DRV0            0x00
  57 #define    IDE_DH_DRV1            0x10
  58 #define  IDE_REG_STATUS           0x0007
  59 #define    IDE_SR_BUSY              0x80
  60 #define    IDE_SR_DRDY              0x40
  61 #define    IDE_SR_DRQ               0x08
  62 #define    IDE_SR_ERR               0x01
  63 #define  IDE_REG_COMMAND          0x0007
  64
  65 /* IDE/ATA commands */
  66 #define    IDE_CMD_RESET            0x08
  67 #define    IDE_CMD_READ             0x20
  68 #define    IDE_CMD_READ_RETRY       0x21
  69 #define    IDE_CMD_WRITE            0x30
  70 #define    IDE_CMD_WRITE_RETRY      0x31
  71 #define    IDE_CMD_PACKET           0xA0
  72 #define    IDE_CMD_READ_MULTIPLE    0xC4
  73 #define    IDE_CMD_WRITE_MULTIPLE   0xC5
  74 #define    IDE_CMD_FLUSH_CACHE      0xE7
  75 #define    IDE_CMD_FLUSH_CACHE_EXT  0xEA
  76 #define    IDE_CMD_IDENT_ATA_DRV    0xEC
  77 #define    IDE_CMD_IDENT_ATAPI_DRV  0xA1
  78
  79 //
  80 //  Access macros for command registers
  81 //  Each macro takes an address of the command port block, and data
  82 //
  83 #define IDEReadError(Address) \
  84   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_ERROR)))
  85 #define IDEWritePrecomp(Address, Data) \
  86   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_PRECOMP), (Data)))
  87 #define IDEReadSectorCount(Address) \
  88   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_CNT)))
  89 #define IDEWriteSectorCount(Address, Data) \
  90   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_CNT), (Data)))
  91 #define IDEReadSectorNum(Address) \
  92   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_NUM)))
  93 #define IDEWriteSectorNum(Address, Data) \
  94   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_NUM), (Data)))
  95 #define IDEReadCylinderLow(Address) \
  96   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_CYL_LOW)))
  97 #define IDEWriteCylinderLow(Address, Data) \
  98   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_CYL_LOW), (Data)))
  99 #define IDEReadCylinderHigh(Address) \
 100   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_CYL_HIGH)))
 101 #define IDEWriteCylinderHigh(Address, Data) \
 102   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_CYL_HIGH), (Data)))
 103 #define IDEReadDriveHead(Address) \
 104   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_DRV_HEAD)))
 105 #define IDEWriteDriveHead(Address, Data) \
 106   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_DRV_HEAD), (Data)))
 107 #define IDEReadStatus(Address) \
 108   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_STATUS)))
 109 #define IDEWriteCommand(Address, Data) \
 110   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_COMMAND), (Data)))
 111
 112
 113 //
 114 //  Data block read and write commands
 115 //
 116 #define IDEReadBlock(Address, Buffer, Count) \
 117   (ScsiPortReadPortBufferUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
 118 #define IDEWriteBlock(Address, Buffer, Count) \
 119   (ScsiPortWritePortBufferUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
 120
 121 #define IDEReadBlock32(Address, Buffer, Count) \
 122   (ScsiPortReadPortBufferUlong((PULONG)((Address) + IDE_REG_DATA_PORT), (PULONG)(Buffer), (Count) / 4))
 123 #define IDEWriteBlock32(Address, Buffer, Count) \
 124   (ScsiPortWritePortBufferUlong((PULONG)((Address) + IDE_REG_DATA_PORT), (PULONG)(Buffer), (Count) / 4))
 125
 126 #define IDEReadWord(Address) \
 127   (ScsiPortReadPortUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT)))
 128
 129 //
 130 //  Access macros for control registers
 131 //  Each macro takes an address of the control port blank and data
 132 //
 133 #define IDEReadAltStatus(Address) \
 134   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_ALT_STATUS)))
 135 #define IDEWriteDriveControl(Address, Data) \
 136   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_DEV_CNTRL), (Data)))
 137
 138
 139
 140 //    IDE_DRIVE_IDENTIFY
 141
 142 typedef struct _IDE_DRIVE_IDENTIFY
 143 {
 144   WORD  ConfigBits;          /*00*/
 145   WORD  LogicalCyls;         /*01*/
 146   WORD  Reserved02;          /*02*/
 147   WORD  LogicalHeads;        /*03*/
 148   WORD  BytesPerTrack;       /*04*/
 149   WORD  BytesPerSector;      /*05*/
 150   WORD  SectorsPerTrack;     /*06*/
 151   BYTE   InterSectorGap;      /*07*/
 152   BYTE   InterSectorGapSize;
 153   BYTE   Reserved08H;         /*08*/
 154   BYTE   BytesInPLO;
 155   WORD  VendorUniqueCnt;     /*09*/
 156   char   SerialNumber[20];    /*10*/
 157   WORD  ControllerType;      /*20*/
 158   WORD  BufferSize;          /*21*/
 159   WORD  ECCByteCnt;          /*22*/
 160   char   FirmwareRev[8];      /*23*/
 161   char   ModelNumber[40];     /*27*/
 162   WORD  RWMultImplemented;   /*47*/
 163   WORD  DWordIo;             /*48*/
 164   WORD  Capabilities;        /*49*/
 165 #define IDE_DRID_STBY_SUPPORTED   0x2000
 166 #define IDE_DRID_IORDY_SUPPORTED  0x0800
 167 #define IDE_DRID_IORDY_DISABLE    0x0400
 168 #define IDE_DRID_LBA_SUPPORTED    0x0200
 169 #define IDE_DRID_DMA_SUPPORTED    0x0100
 170   WORD  Reserved50;          /*50*/
 171   WORD  MinPIOTransTime;     /*51*/
 172   WORD  MinDMATransTime;     /*52*/
 173   WORD  TMFieldsValid;       /*53*/
 174   WORD  TMCylinders;         /*54*/
 175   WORD  TMHeads;             /*55*/
 176   WORD  TMSectorsPerTrk;     /*56*/
 177   WORD  TMCapacityLo;        /*57*/
 178   WORD  TMCapacityHi;        /*58*/
 179   WORD  RWMultCurrent;       /*59*/
 180   WORD  TMSectorCountLo;     /*60*/
 181   WORD  TMSectorCountHi;     /*61*/
 182   WORD  Reserved62[193];     /*62*/
 183   WORD  Checksum;            /*255*/
 184 } IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
 185
 186 #ifdef __cplusplus
 187 }
 188 #endif
 189
 190 #endif  /*  __ATAPT_H  */
 191
 192