2 // ATAPI.H - defines and typedefs for the IDE Driver module.
12 #define IDE_MAXIMUM_DEVICES 8
14 #define IDE_MAX_NAME_LENGTH 50
16 #define IDE_SECTOR_BUF_SZ 512
17 #define IDE_MAX_SECTORS_PER_XFER 256
18 #define IDE_MAX_RESET_RETRIES 10000
19 #define IDE_MAX_POLL_RETRIES 100000
20 #define IDE_MAX_WRITE_RETRIES 1000
21 #define IDE_MAX_BUSY_RETRIES 50000
22 #define IDE_MAX_DRQ_RETRIES 10000
23 //#define IDE_MAX_CMD_RETRIES 1
24 #define IDE_MAX_CMD_RETRIES 0
25 #define IDE_CMD_TIMEOUT 5
26 #define IDE_RESET_PULSE_LENGTH 500 /* maybe a little too long */
27 #define IDE_RESET_BUSY_TIMEOUT 120
28 #define IDE_RESET_DRDY_TIMEOUT 120
30 // Control Block offsets and masks
31 #define IDE_REG_ALT_STATUS 0x0000
32 #define IDE_REG_DEV_CNTRL 0x0000 /* device control register */
33 #define IDE_DC_SRST 0x04 /* drive reset (both drives) */
34 #define IDE_DC_nIEN 0x02 /* IRQ enable (active low) */
35 #define IDE_REG_DRV_ADDR 0x0001
37 // Command Block offsets and masks
38 #define IDE_REG_DATA_PORT 0x0000
39 #define IDE_REG_ERROR 0x0001 /* error register */
40 #define IDE_ER_AMNF 0x01 /* addr mark not found */
41 #define IDE_ER_TK0NF 0x02 /* track 0 not found */
42 #define IDE_ER_ABRT 0x04 /* command aborted */
43 #define IDE_ER_MCR 0x08 /* media change requested */
44 #define IDE_ER_IDNF 0x10 /* ID not found */
45 #define IDE_ER_MC 0x20 /* Media changed */
46 #define IDE_ER_UNC 0x40 /* Uncorrectable data error */
47 #define IDE_REG_PRECOMP 0x0001
48 #define IDE_REG_SECTOR_CNT 0x0002
49 #define IDE_REG_SECTOR_NUM 0x0003
50 #define IDE_REG_CYL_LOW 0x0004
51 #define IDE_REG_CYL_HIGH 0x0005
52 #define IDE_REG_DRV_HEAD 0x0006
53 #define IDE_DH_FIXED 0xA0
54 #define IDE_DH_LBA 0x40
55 #define IDE_DH_HDMASK 0x0F
56 #define IDE_DH_DRV0 0x00
57 #define IDE_DH_DRV1 0x10
58 #define IDE_REG_STATUS 0x0007
59 #define IDE_SR_BUSY 0x80
60 #define IDE_SR_DRDY 0x40
61 #define IDE_SR_DRQ 0x08
62 #define IDE_SR_ERR 0x01
63 #define IDE_REG_COMMAND 0x0007
64 #define IDE_CMD_RESET 0x08
65 #define IDE_CMD_READ 0x20
66 #define IDE_CMD_READ_RETRY 0x21
67 #define IDE_CMD_WRITE 0x30
68 #define IDE_CMD_WRITE_RETRY 0x31
69 #define IDE_CMD_IDENT_ATA_DRV 0xEC
70 #define IDE_CMD_IDENT_ATAPI_DRV 0xA1
72 // Access macros for command registers
73 // Each macro takes an address of the command port block, and data
75 #define IDEReadError(Address) \
76 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_ERROR)))
77 #define IDEWritePrecomp(Address, Data) \
78 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_PRECOMP), (Data)))
79 #define IDEReadSectorCount(Address) \
80 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_CNT)))
81 #define IDEWriteSectorCount(Address, Data) \
82 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_CNT), (Data)))
83 #define IDEReadSectorNum(Address) \
84 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_NUM)))
85 #define IDEWriteSectorNum(Address, Data) \
86 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_NUM), (Data)))
87 #define IDEReadCylinderLow(Address) \
88 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_CYL_LOW)))
89 #define IDEWriteCylinderLow(Address, Data) \
90 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_CYL_LOW), (Data)))
91 #define IDEReadCylinderHigh(Address) \
92 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_CYL_HIGH)))
93 #define IDEWriteCylinderHigh(Address, Data) \
94 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_CYL_HIGH), (Data)))
95 #define IDEReadDriveHead(Address) \
96 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_DRV_HEAD)))
97 #define IDEWriteDriveHead(Address, Data) \
98 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_DRV_HEAD), (Data)))
99 #define IDEReadStatus(Address) \
100 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_STATUS)))
101 #define IDEWriteCommand(Address, Data) \
102 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_COMMAND), (Data)))
106 // Data block read and write commands
108 #define IDEReadBlock(Address, Buffer, Count) \
109 (ScsiPortReadPortBufferUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
110 #define IDEWriteBlock(Address, Buffer, Count) \
111 (ScsiPortWritePortBufferUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
114 // Access macros for control registers
115 // Each macro takes an address of the control port blank and data
117 #define IDEReadAltStatus(Address) \
118 (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_ALT_STATUS)))
119 #define IDEWriteDriveControl(Address, Data) \
120 (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_DEV_CNTRL), (Data)))
124 // IDE_DRIVE_IDENTIFY
126 typedef struct _IDE_DRIVE_IDENTIFY
128 WORD ConfigBits; /*00*/
129 WORD LogicalCyls; /*01*/
130 WORD Reserved02; /*02*/
131 WORD LogicalHeads; /*03*/
132 WORD BytesPerTrack; /*04*/
133 WORD BytesPerSector; /*05*/
134 WORD SectorsPerTrack; /*06*/
135 BYTE InterSectorGap; /*07*/
136 BYTE InterSectorGapSize;
137 BYTE Reserved08H; /*08*/
139 WORD VendorUniqueCnt; /*09*/
140 char SerialNumber[20]; /*10*/
141 WORD ControllerType; /*20*/
142 WORD BufferSize; /*21*/
143 WORD ECCByteCnt; /*22*/
144 char FirmwareRev[8]; /*23*/
145 char ModelNumber[40]; /*27*/
146 WORD RWMultImplemented; /*47*/
147 WORD Reserved48; /*48*/
148 WORD Capabilities; /*49*/
149 #define IDE_DRID_STBY_SUPPORTED 0x2000
150 #define IDE_DRID_IORDY_SUPPORTED 0x0800
151 #define IDE_DRID_IORDY_DISABLE 0x0400
152 #define IDE_DRID_LBA_SUPPORTED 0x0200
153 #define IDE_DRID_DMA_SUPPORTED 0x0100
154 WORD Reserved50; /*50*/
155 WORD MinPIOTransTime; /*51*/
156 WORD MinDMATransTime; /*52*/
157 WORD TMFieldsValid; /*53*/
158 WORD TMCylinders; /*54*/
160 WORD TMSectorsPerTrk; /*56*/
161 WORD TMCapacityLo; /*57*/
162 WORD TMCapacityHi; /*58*/
163 WORD Reserved59; /*59*/
164 WORD TMSectorCountLo; /*60*/
165 WORD TMSectorCountHi; /*61*/
166 WORD Reserved62[193]; /*62*/
167 WORD Checksum; /*255*/
168 } IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
175 #endif /* __ATAPT_H */