drivers/storage/atapi/atapi.h

   1 //
   2 //  ATAPI.H - defines and typedefs for the IDE Driver module.
   3 //
   4
   5 #ifndef __ATAPI_H
   6 #define __ATAPI_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #define  IDE_MAXIMUM_DEVICES    8
  13
  14 #define IDE_MAX_NAME_LENGTH     50
  15
  16 #define  IDE_SECTOR_BUF_SZ         512
  17 #define  IDE_MAX_SECTORS_PER_XFER  256
  18 #define  IDE_MAX_RESET_RETRIES     10000
  19 #define  IDE_MAX_POLL_RETRIES      100000
  20 #define  IDE_MAX_WRITE_RETRIES     1000
  21 #define  IDE_MAX_BUSY_RETRIES      50000
  22 #define  IDE_MAX_DRQ_RETRIES       10000
  23 //#define  IDE_MAX_CMD_RETRIES       1
  24 #define  IDE_MAX_CMD_RETRIES       0
  25 #define  IDE_CMD_TIMEOUT           5
  26 #define  IDE_RESET_PULSE_LENGTH    500  /* maybe a little too long */
  27 #define  IDE_RESET_BUSY_TIMEOUT    120
  28 #define  IDE_RESET_DRDY_TIMEOUT    120
  29
  30 // Control Block offsets and masks
  31 #define  IDE_REG_ALT_STATUS     0x0000
  32 #define  IDE_REG_DEV_CNTRL      0x0000  /* device control register */
  33 #define    IDE_DC_SRST            0x04  /* drive reset (both drives) */
  34 #define    IDE_DC_nIEN            0x02  /* IRQ enable (active low) */
  35 #define  IDE_REG_DRV_ADDR       0x0001
  36
  37 // Command Block offsets and masks
  38 #define  IDE_REG_DATA_PORT      0x0000
  39 #define  IDE_REG_ERROR          0x0001  /* error register */
  40 #define    IDE_ER_AMNF            0x01  /* addr mark not found */
  41 #define    IDE_ER_TK0NF           0x02  /* track 0 not found */
  42 #define    IDE_ER_ABRT            0x04  /* command aborted */
  43 #define    IDE_ER_MCR             0x08  /* media change requested */
  44 #define    IDE_ER_IDNF            0x10  /* ID not found */
  45 #define    IDE_ER_MC              0x20  /* Media changed */
  46 #define    IDE_ER_UNC             0x40  /* Uncorrectable data error */
  47 #define  IDE_REG_PRECOMP        0x0001
  48 #define  IDE_REG_SECTOR_CNT     0x0002
  49 #define  IDE_REG_SECTOR_NUM     0x0003
  50 #define  IDE_REG_CYL_LOW        0x0004
  51 #define  IDE_REG_CYL_HIGH       0x0005
  52 #define  IDE_REG_DRV_HEAD       0x0006
  53 #define    IDE_DH_FIXED           0xA0
  54 #define    IDE_DH_LBA             0x40
  55 #define    IDE_DH_HDMASK          0x0F
  56 #define    IDE_DH_DRV0            0x00
  57 #define    IDE_DH_DRV1            0x10
  58 #define  IDE_REG_STATUS           0x0007
  59 #define    IDE_SR_BUSY              0x80
  60 #define    IDE_SR_DRDY              0x40
  61 #define    IDE_SR_DRQ               0x08
  62 #define    IDE_SR_ERR               0x01
  63 #define  IDE_REG_COMMAND          0x0007
  64
  65 /* IDE/ATA commands */
  66 #define    IDE_CMD_RESET            0x08
  67 #define    IDE_CMD_READ             0x20
  68 #define    IDE_CMD_READ_RETRY       0x21
  69 #define    IDE_CMD_WRITE            0x30
  70 #define    IDE_CMD_WRITE_RETRY      0x31
  71 #define    IDE_CMD_PACKET           0xA0
  72 #define    IDE_CMD_READ_MULTIPLE    0xC4
  73 #define    IDE_CMD_WRITE_MULTIPLE   0xC5
  74 #define    IDE_CMD_FLUSH_CACHE      0xE7
  75 #define    IDE_CMD_FLUSH_CACHE_EXT  0xEA
  76 #define    IDE_CMD_IDENT_ATA_DRV    0xEC
  77 #define    IDE_CMD_IDENT_ATAPI_DRV  0xA1
  78 #define    IDE_CMD_GET_MEDIA_STATUS 0xDA
  79
  80 //
  81 //  Access macros for command registers
  82 //  Each macro takes an address of the command port block, and data
  83 //
  84 #define IDEReadError(Address) \
  85   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_ERROR)))
  86 #define IDEWritePrecomp(Address, Data) \
  87   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_PRECOMP), (Data)))
  88 #define IDEReadSectorCount(Address) \
  89   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_CNT)))
  90 #define IDEWriteSectorCount(Address, Data) \
  91   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_CNT), (Data)))
  92 #define IDEReadSectorNum(Address) \
  93   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_NUM)))
  94 #define IDEWriteSectorNum(Address, Data) \
  95   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_SECTOR_NUM), (Data)))
  96 #define IDEReadCylinderLow(Address) \
  97   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_CYL_LOW)))
  98 #define IDEWriteCylinderLow(Address, Data) \
  99   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_CYL_LOW), (Data)))
 100 #define IDEReadCylinderHigh(Address) \
 101   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_CYL_HIGH)))
 102 #define IDEWriteCylinderHigh(Address, Data) \
 103   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_CYL_HIGH), (Data)))
 104 #define IDEReadDriveHead(Address) \
 105   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_DRV_HEAD)))
 106 #define IDEWriteDriveHead(Address, Data) \
 107   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_DRV_HEAD), (Data)))
 108 #define IDEReadStatus(Address) \
 109   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_STATUS)))
 110 #define IDEWriteCommand(Address, Data) \
 111   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_COMMAND), (Data)))
 112
 113
 114 //
 115 //  Data block read and write commands
 116 //
 117 #define IDEReadBlock(Address, Buffer, Count) \
 118   (ScsiPortReadPortBufferUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
 119 #define IDEWriteBlock(Address, Buffer, Count) \
 120   (ScsiPortWritePortBufferUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
 121
 122 #define IDEReadBlock32(Address, Buffer, Count) \
 123   (ScsiPortReadPortBufferUlong((PULONG)((Address) + IDE_REG_DATA_PORT), (PULONG)(Buffer), (Count) / 4))
 124 #define IDEWriteBlock32(Address, Buffer, Count) \
 125   (ScsiPortWritePortBufferUlong((PULONG)((Address) + IDE_REG_DATA_PORT), (PULONG)(Buffer), (Count) / 4))
 126
 127 #define IDEReadWord(Address) \
 128   (ScsiPortReadPortUshort((PUSHORT)((Address) + IDE_REG_DATA_PORT)))
 129
 130 //
 131 //  Access macros for control registers
 132 //  Each macro takes an address of the control port blank and data
 133 //
 134 #define IDEReadAltStatus(Address) \
 135   (ScsiPortReadPortUchar((PUCHAR)((Address) + IDE_REG_ALT_STATUS)))
 136 #define IDEWriteDriveControl(Address, Data) \
 137   (ScsiPortWritePortUchar((PUCHAR)((Address) + IDE_REG_DEV_CNTRL), (Data)))
 138
 139
 140
 141 //    IDE_DRIVE_IDENTIFY
 142
 143 typedef struct _IDE_DRIVE_IDENTIFY
 144 {
 145   WORD  ConfigBits;          /*00*/
 146   WORD  LogicalCyls;         /*01*/
 147   WORD  Reserved02;          /*02*/
 148   WORD  LogicalHeads;        /*03*/
 149   WORD  BytesPerTrack;       /*04*/
 150   WORD  BytesPerSector;      /*05*/
 151   WORD  SectorsPerTrack;     /*06*/
 152   BYTE   InterSectorGap;      /*07*/
 153   BYTE   InterSectorGapSize;
 154   BYTE   Reserved08H;         /*08*/
 155   BYTE   BytesInPLO;
 156   WORD  VendorUniqueCnt;     /*09*/
 157   char   SerialNumber[20];    /*10*/
 158   WORD  ControllerType;      /*20*/
 159   WORD  BufferSize;          /*21*/
 160   WORD  ECCByteCnt;          /*22*/
 161   char   FirmwareRev[8];      /*23*/
 162   char   ModelNumber[40];     /*27*/
 163   WORD  RWMultImplemented;   /*47*/
 164   WORD  DWordIo;             /*48*/
 165   WORD  Capabilities;        /*49*/
 166 #define IDE_DRID_STBY_SUPPORTED   0x2000
 167 #define IDE_DRID_IORDY_SUPPORTED  0x0800
 168 #define IDE_DRID_IORDY_DISABLE    0x0400
 169 #define IDE_DRID_LBA_SUPPORTED    0x0200
 170 #define IDE_DRID_DMA_SUPPORTED    0x0100
 171   WORD  Reserved50;          /*50*/
 172   WORD  MinPIOTransTime;     /*51*/
 173   WORD  MinDMATransTime;     /*52*/
 174   WORD  TMFieldsValid;       /*53*/
 175   WORD  TMCylinders;         /*54*/
 176   WORD  TMHeads;             /*55*/
 177   WORD  TMSectorsPerTrk;     /*56*/
 178   WORD  TMCapacityLo;        /*57*/
 179   WORD  TMCapacityHi;        /*58*/
 180   WORD  RWMultCurrent;       /*59*/
 181   WORD  TMSectorCountLo;     /*60*/
 182   WORD  TMSectorCountHi;     /*61*/
 183   WORD  DmaModes;            /*62*/
 184   WORD  MultiDmaModes;       /*63*/
 185   WORD  Reserved64[5];       /*64*/
 186   WORD  Reserved69[2];       /*69*/
 187   WORD  Reserved71[4];       /*71*/
 188   WORD  MaxQueueDepth;       /*75*/
 189   WORD  Reserved76[4];       /*76*/
 190   WORD  MajorRevision;       /*80*/
 191   WORD  MinorRevision;       /*81*/
 192   WORD  SupportedFeatures82; /*82*/
 193   WORD  SupportedFeatures83; /*83*/
 194   WORD  SupportedFeatures84; /*84*/
 195   WORD  EnabledFeatures85;   /*85*/
 196   WORD  EnabledFeatures86;   /*86*/
 197   WORD  EnabledFeatures87;   /*87*/
 198   WORD  UltraDmaModes;       /*88*/
 199   WORD  Reserved89[11];      /*89*/
 200   WORD  Max48BitAddress[4];  /*100*/
 201   WORD  Reserved104[151];    /*104*/
 202   WORD  Checksum;            /*255*/
 203 } IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
 204
 205
 206 /* Special ATAPI commands */
 207
 208 #define ATAPI_FORMAT_UNIT       0x24
 209 #define ATAPI_MODE_SELECT       0x55
 210 #define ATAPI_MODE_SENSE        0x5A
 211
 212
 213 /* Special ATAPI_MODE_SELECT (12 bytes) command block */
 214
 215 typedef struct _ATAPI_MODE_SELECT12
 216 {
 217   UCHAR OperationCode;
 218   UCHAR Reserved1:4;
 219   UCHAR PFBit:1;
 220   UCHAR Reserved2:3;
 221   UCHAR Reserved3[5];
 222   UCHAR ParameterListLengthMsb;
 223   UCHAR ParameterListLengthLsb;
 224   UCHAR Reserved4[3];
 225 } ATAPI_MODE_SELECT12, *PATAPI_MODE_SELECT12;
 226
 227
 228 /* Special ATAPI_MODE_SENSE (12 bytes) command block */
 229
 230 typedef struct _ATAPI_MODE_SENSE12
 231 {
 232   UCHAR OperationCode;
 233   UCHAR Reserved1;
 234   UCHAR PageCode:6;
 235   UCHAR Pc:2;
 236   UCHAR Reserved2[4];
 237   UCHAR ParameterListLengthMsb;
 238   UCHAR ParameterListLengthLsb;
 239   UCHAR Reserved3[3];
 240 } ATAPI_MODE_SENSE12, *PATAPI_MODE_SENSE12;
 241
 242 #ifdef __cplusplus
 243 }
 244 #endif
 245
 246 #endif  /*  __ATAPT_H  */
 247
 248