drivers/storage/disk/disk.h

   1 //
   2 //  IDE.H - defines and typedefs for the IDE Driver module.
   3 //
   4
   5 #ifndef __IDE_H
   6 #define __IDE_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #define  IDE_MAXIMUM_DEVICES    8
  13
  14 #define IDE_MAX_NAME_LENGTH     50
  15
  16 #define  IDE_SECTOR_BUF_SZ         512
  17 #define  IDE_MAX_SECTORS_PER_XFER  256
  18 #define  IDE_MAX_RESET_RETRIES     10000
  19 #define  IDE_MAX_POLL_RETRIES      100000
  20 #define  IDE_MAX_WRITE_RETRIES     1000
  21 #define  IDE_MAX_BUSY_RETRIES      100
  22 //#define  IDE_MAX_BUSY_RETRIES       100000
  23 #define  IDE_MAX_DRQ_RETRIES       10000
  24 //#define  IDE_MAX_CMD_RETRIES       1
  25 #define  IDE_MAX_CMD_RETRIES       0
  26 #define  IDE_CMD_TIMEOUT           5
  27 #define  IDE_RESET_PULSE_LENGTH    500  /* maybe a little too long */
  28 #define  IDE_RESET_BUSY_TIMEOUT    31
  29 #define  IDE_RESET_DRDY_TIMEOUT    120
  30
  31 // Control Block offsets and masks
  32 #define  IDE_REG_ALT_STATUS     0x0000
  33 #define  IDE_REG_DEV_CNTRL      0x0000  /* device control register */
  34 #define    IDE_DC_SRST            0x04  /* drive reset (both drives) */
  35 #define    IDE_DC_nIEN            0x02  /* IRQ enable (active low) */
  36 #define  IDE_REG_DRV_ADDR       0x0001
  37
  38 // Command Block offsets and masks
  39 #define  IDE_REG_DATA_PORT      0x0000
  40 #define  IDE_REG_ERROR          0x0001  /* error register */
  41 #define    IDE_ER_AMNF            0x01  /* addr mark not found */
  42 #define    IDE_ER_TK0NF           0x02  /* track 0 not found */
  43 #define    IDE_ER_ABRT            0x04  /* command aborted */
  44 #define    IDE_ER_MCR             0x08  /* media change requested */
  45 #define    IDE_ER_IDNF            0x10  /* ID not found */
  46 #define    IDE_ER_MC              0x20  /* Media changed */
  47 #define    IDE_ER_UNC             0x40  /* Uncorrectable data error */
  48 #define  IDE_REG_PRECOMP        0x0001
  49 #define  IDE_REG_SECTOR_CNT     0x0002
  50 #define  IDE_REG_SECTOR_NUM     0x0003
  51 #define  IDE_REG_CYL_LOW        0x0004
  52 #define  IDE_REG_CYL_HIGH       0x0005
  53 #define  IDE_REG_DRV_HEAD       0x0006
  54 #define    IDE_DH_FIXED           0xA0
  55 #define    IDE_DH_LBA             0x40
  56 #define    IDE_DH_HDMASK          0x0F
  57 #define    IDE_DH_DRV0            0x00
  58 #define    IDE_DH_DRV1            0x10
  59 #define  IDE_REG_STATUS         0x0007
  60 #define    IDE_SR_BUSY            0x80
  61 #define    IDE_SR_DRDY            0x40
  62 #define    IDE_SR_DRQ             0x08
  63 #define    IDE_SR_ERR             0x01
  64 #define  IDE_REG_COMMAND        0x0007
  65 #define    IDE_CMD_READ           0x20
  66 #define    IDE_CMD_READ_RETRY     0x21
  67 #define    IDE_CMD_WRITE          0x30
  68 #define    IDE_CMD_WRITE_RETRY    0x31
  69 #define    IDE_CMD_IDENT_DRV      0xEC
  70
  71 //
  72 //  Access macros for command registers
  73 //  Each macro takes an address of the command port block, and data
  74 //
  75 #define IDEReadError(Address) \
  76   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_ERROR)))
  77 #define IDEWritePrecomp(Address, Data) \
  78   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_PRECOMP), (Data)))
  79 #define IDEReadSectorCount(Address) \
  80   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_SECTOR_CNT)))
  81 #define IDEWriteSectorCount(Address, Data) \
  82   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_SECTOR_CNT), (Data)))
  83 #define IDEReadSectorNum(Address) \
  84   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_SECTOR_NUM)))
  85 #define IDEWriteSectorNum(Address, Data) \
  86   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_SECTOR_NUM), (Data)))
  87 #define IDEReadCylinderLow(Address) \
  88   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_CYL_LOW)))
  89 #define IDEWriteCylinderLow(Address, Data) \
  90   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_CYL_LOW), (Data)))
  91 #define IDEReadCylinderHigh(Address) \
  92   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_CYL_HIGH)))
  93 #define IDEWriteCylinderHigh(Address, Data) \
  94   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_CYL_HIGH), (Data)))
  95 #define IDEReadDriveHead(Address) \
  96   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_DRV_HEAD)))
  97 #define IDEWriteDriveHead(Address, Data) \
  98   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_DRV_HEAD), (Data)))
  99 #define IDEReadStatus(Address) \
 100   (READ_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_STATUS)))
 101 #define IDEWriteCommand(Address, Data) \
 102   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_COMMAND), (Data)))
 103
 104
 105 //
 106 //  Data block read and write commands
 107 //
 108 #define IDEReadBlock(Address, Buffer, Count) \
 109   (READ_PORT_BUFFER_USHORT((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
 110 #define IDEWriteBlock(Address, Buffer, Count) \
 111   (WRITE_PORT_BUFFER_USHORT((PUSHORT)((Address) + IDE_REG_DATA_PORT), (PUSHORT)(Buffer), (Count) / 2))
 112
 113 //
 114 //  Access macros for control registers
 115 //  Each macro takes an address of the control port blank and data
 116 //
 117 #define IDEWriteDriveControl(Address, Data) \
 118   (WRITE_PORT_UCHAR((PUCHAR)((Address) + IDE_REG_DEV_CNTRL), (Data)))
 119
 120 //    IDE_DEVICE_EXTENSION
 121 //
 122 //  DESCRIPTION:
 123 //    Extension to be placed in each device object
 124 //
 125 //  ACCESS:
 126 //    Allocated from NON-PAGED POOL
 127 //    Available at any IRQL
 128 //
 129
 130 typedef struct _IDE_DEVICE_EXTENSION {
 131   PDEVICE_OBJECT         DeviceObject;
 132   PCONTROLLER_OBJECT     ControllerObject;
 133   struct _IDE_DEVICE_EXTESION  *DiskExtension;
 134   int                    UnitNumber;
 135   BOOLEAN                LBASupported;
 136   BOOLEAN                DMASupported;
 137   int                    BytesPerSector;
 138   int                    LogicalHeads;
 139   int                    SectorsPerLogCyl;
 140   int                    SectorsPerLogTrk;
 141   int                    Offset;
 142   int                    Size;
 143
 144   int                    Operation;
 145   ULONG                  BytesRequested;
 146   ULONG                  BytesToTransfer;
 147   ULONG                  BytesRemaining;
 148   ULONG                  StartingSector;
 149   int                    SectorsTransferred;
 150   BYTE                  *TargetAddress;
 151
 152 } IDE_DEVICE_EXTENSION, *PIDE_DEVICE_EXTENSION;
 153
 154 //    IDE_TIMER_STATES
 155 //
 156 //  DESCRIPTION:
 157 //    An enumeration containing the states in the timer DFA
 158 //
 159
 160 typedef enum _IDE_TIMER_STATES {
 161   IDETimerIdle,
 162   IDETimerCmdWait,
 163   IDETimerResetWaitForBusyNegate,
 164   IDETimerResetWaitForDrdyAssert
 165 } IDE_TIMER_STATES;
 166
 167 //    IDE_CONTROLLER_EXTENSION
 168 //
 169 //  DESCRIPTION:
 170 //    Driver-defined structure used to hold miscellaneous controller information.
 171 //
 172 //  ACCESS:
 173 //    Allocated from NON-PAGED POOL
 174 //    Available at any IRQL
 175 //
 176
 177 typedef struct _IDE_CONTROLLER_EXTENSION {
 178   KSPIN_LOCK             SpinLock;
 179   int                    Number;
 180   int                    Vector;
 181   int                    CommandPortBase;
 182   int                    ControlPortBase;
 183   BOOLEAN                DMASupported;
 184   BOOLEAN                ControllerInterruptBug;
 185   PKINTERRUPT            Interrupt;
 186
 187   BOOLEAN                OperationInProgress;
 188   BYTE                   DeviceStatus;
 189   PIDE_DEVICE_EXTENSION  DeviceForOperation;
 190   PIRP                   CurrentIrp;
 191   int                    Retries;
 192
 193   IDE_TIMER_STATES       TimerState;
 194   LONG                   TimerCount;
 195   PDEVICE_OBJECT         TimerDevice;
 196
 197 } IDE_CONTROLLER_EXTENSION, *PIDE_CONTROLLER_EXTENSION;
 198
 199 //    IDE_DRIVE_IDENTIFY
 200
 201 typedef struct _IDE_DRIVE_IDENTIFY {
 202   WORD  ConfigBits;          /*00*/
 203   WORD  LogicalCyls;         /*01*/
 204   WORD  Reserved02;          /*02*/
 205   WORD  LogicalHeads;        /*03*/
 206   WORD  BytesPerTrack;       /*04*/
 207   WORD  BytesPerSector;      /*05*/
 208   WORD  SectorsPerTrack;     /*06*/
 209   BYTE   InterSectorGap;      /*07*/
 210   BYTE   InterSectorGapSize;
 211   BYTE   Reserved08H;         /*08*/
 212   BYTE   BytesInPLO;
 213   WORD  VendorUniqueCnt;     /*09*/
 214   char   SerialNumber[20];    /*10*/
 215   WORD  ControllerType;      /*20*/
 216   WORD  BufferSize;          /*21*/
 217   WORD  ECCByteCnt;          /*22*/
 218   char   FirmwareRev[8];      /*23*/
 219   char   ModelNumber[40];     /*27*/
 220   WORD  RWMultImplemented;   /*47*/
 221   WORD  Reserved48;          /*48*/
 222   WORD  Capabilities;        /*49*/
 223 #define IDE_DRID_STBY_SUPPORTED   0x2000
 224 #define IDE_DRID_IORDY_SUPPORTED  0x0800
 225 #define IDE_DRID_IORDY_DISABLE    0x0400
 226 #define IDE_DRID_LBA_SUPPORTED    0x0200
 227 #define IDE_DRID_DMA_SUPPORTED    0x0100
 228   WORD  Reserved50;          /*50*/
 229   WORD  MinPIOTransTime;     /*51*/
 230   WORD  MinDMATransTime;     /*52*/
 231   WORD  TMFieldsValid;       /*53*/
 232   WORD  TMCylinders;         /*54*/
 233   WORD  TMHeads;             /*55*/
 234   WORD  TMSectorsPerTrk;     /*56*/
 235   WORD  TMCapacityLo;        /*57*/
 236   WORD  TMCapacityHi;        /*58*/
 237   WORD  Reserved59;          /*59*/
 238   WORD  TMSectorCountLo;     /*60*/
 239   WORD  TMSectorCountHi;     /*61*/
 240   WORD  Reserved62[194];     /*62*/
 241 } IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
 242
 243
 244 #ifdef __cplusplus
 245 }
 246 #endif
 247
 248 #endif  /*  __IDE_H  */
 249
 250