3 * COPYRIGHT: See COPYING in the top level directory
4 * PROJECT: ReactOS kernel
5 * FILE: include/ddk/haltypes.h
6 * PURPOSE: HAL provided defintions for device drivers
7 * PROGRAMMER: David Welch (welch@mcmail.com)
9 * 23/06/98: Taken from linux system.h
13 #ifndef __INCLUDE_DDK_HALTYPES_H
14 #define __INCLUDE_DDK_HALTYPES_H
17 /* HalReturnToFirmware */
18 #define FIRMWARE_HALT 1
19 #define FIRMWARE_REBOOT 3
23 DEVICE_DESCRIPTION_VERSION,
24 DEVICE_DESCRIPTION_VERSION1,
27 typedef ULONG DMA_WIDTH;
28 typedef ULONG DMA_SPEED;
31 * PURPOSE: Types for HalGetBusData
33 typedef enum _BUS_DATA_TYPE
35 ConfigurationSpaceUndefined = -1,
48 } BUS_DATA_TYPE, *PBUS_DATA_TYPE;
50 typedef struct _DEVICE_DESCRIPTION
54 BOOLEAN ScatterGather;
56 BOOLEAN AutoInitialize;
57 BOOLEAN Dma32BitAddress;
63 INTERFACE_TYPE InterfaceType;
68 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
71 /* PCI bus definitions */
73 #define PCI_TYPE0_ADDRESSES 6
74 #define PCI_TYPE1_ADDRESSES 2
75 #define PCI_TYPE2_ADDRESSES 5
77 typedef struct _PCI_COMMON_CONFIG
79 USHORT VendorID; /* read-only */
80 USHORT DeviceID; /* read-only */
83 UCHAR RevisionID; /* read-only */
84 UCHAR ProgIf; /* read-only */
85 UCHAR SubClass; /* read-only */
86 UCHAR BaseClass; /* read-only */
87 UCHAR CacheLineSize; /* read-only */
88 UCHAR LatencyTimer; /* read-only */
89 UCHAR HeaderType; /* read-only */
93 struct _PCI_HEADER_TYPE_0
95 ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
103 UCHAR InterruptPin; /* read-only */
104 UCHAR MinimumGrant; /* read-only */
105 UCHAR MaximumLatency; /* read-only */
108 /* PCI to PCI Bridge */
109 struct _PCI_HEADER_TYPE_1
111 ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
114 UCHAR SubordinateBus;
115 UCHAR SecondaryLatency;
118 USHORT SecondaryStatus;
122 USHORT PrefetchLimit;
123 ULONG PrefetchBaseUpper32;
124 ULONG PrefetchLimitUpper32;
125 USHORT IOBaseUpper16;
126 USHORT IOLimitUpper16;
127 UCHAR CapabilitiesPtr;
129 ULONG ROMBaseAddress;
132 USHORT BridgeControl;
135 /* PCI to CARDBUS Bridge */
136 struct _PCI_HEADER_TYPE_2
138 ULONG SocketRegistersBaseAddress;
139 UCHAR CapabilitiesPtr;
141 USHORT SecondaryStatus;
144 UCHAR SubordinateBus;
145 UCHAR SecondaryLatency;
150 } Range[PCI_TYPE2_ADDRESSES-1];
153 USHORT BridgeControl;
156 UCHAR DeviceSpecific[192];
157 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
159 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
161 #define PCI_MAX_DEVICES 32
162 #define PCI_MAX_FUNCTION 8
164 #define PCI_INVALID_VENDORID 0xFFFF
167 /* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
169 #define PCI_MULTIFUNCTION 0x80
170 #define PCI_DEVICE_TYPE 0x00
171 #define PCI_BRIDGE_TYPE 0x01
174 /* Bit encodings for PCI_COMMON_CONFIG.Command */
176 #define PCI_ENABLE_IO_SPACE 0x0001
177 #define PCI_ENABLE_MEMORY_SPACE 0x0002
178 #define PCI_ENABLE_BUS_MASTER 0x0004
179 #define PCI_ENABLE_SPECIAL_CYCLES 0x0008
180 #define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
181 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
182 #define PCI_ENABLE_PARITY 0x0040
183 #define PCI_ENABLE_WAIT_CYCLE 0x0080
184 #define PCI_ENABLE_SERR 0x0100
185 #define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
188 /* Bit encodings for PCI_COMMON_CONFIG.Status */
190 #define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
191 #define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
192 #define PCI_STATUS_DEVSEL 0x0600 /* 2 bits wide */
193 #define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
194 #define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
195 #define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
196 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
197 #define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
200 /* PCI device classes */
202 #define PCI_CLASS_PRE_20 0x00
203 #define PCI_CLASS_MASS_STORAGE_CTLR 0x01
204 #define PCI_CLASS_NETWORK_CTLR 0x02
205 #define PCI_CLASS_DISPLAY_CTLR 0x03
206 #define PCI_CLASS_MULTIMEDIA_DEV 0x04
207 #define PCI_CLASS_MEMORY_CTLR 0x05
208 #define PCI_CLASS_BRIDGE_DEV 0x06
209 #define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07
210 #define PCI_CLASS_BASE_SYSTEM_DEV 0x08
211 #define PCI_CLASS_INPUT_DEV 0x09
212 #define PCI_CLASS_DOCKING_STATION 0x0a
213 #define PCI_CLASS_PROCESSOR 0x0b
214 #define PCI_CLASS_SERIAL_BUS_CTLR 0x0c
217 /* PCI device subclasses for class 1 (mass storage controllers)*/
219 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
220 #define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
221 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
222 #define PCI_SUBCLASS_MSC_IPI_CTLR 0x03
223 #define PCI_SUBCLASS_MSC_RAID_CTLR 0x04
224 #define PCI_SUBCLASS_MSC_OTHER 0x80
227 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
229 #define PCI_ADDRESS_IO_SPACE 0x00000001
230 #define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006
231 #define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
233 #define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc
234 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0
235 #define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800
237 #define PCI_TYPE_32BIT 0
238 #define PCI_TYPE_20BIT 2
239 #define PCI_TYPE_64BIT 4
242 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
244 #define PCI_ROMADDRESS_ENABLED 0x00000001
248 typedef struct _PCI_SLOT_NUMBER
254 ULONG DeviceNumber:5;
255 ULONG FunctionNumber:3;
260 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
263 /* MicroChannel bus data */
265 typedef struct _CM_MCA_POS_DATA
272 } CM_MCA_POS_DATA, *PCM_MCA_POS_DATA;
275 /* Hal dispatch table */
277 typedef enum _HAL_QUERY_INFORMATION_CLASS
279 HalInstalledBusInformation,
280 HalProfileSourceInformation,
281 HalSystemDockInformation,
283 HalProcessorSpeedInformation,
284 HalCallbackInformation,
285 HalMapRegisterInformation,
286 HalMcaLogInformation,
287 HalFrameBufferCachingInformation,
288 HalDisplayBiosInformation
289 /* information levels >= 0x8000000 reserved for OEM use */
290 } HAL_QUERY_INFORMATION_CLASS, *PHAL_QUERY_INFORMATION_CLASS;
293 typedef enum _HAL_SET_INFORMATION_CLASS
295 HalProfileSourceInterval,
296 HalProfileSourceInterruptHandler,
298 } HAL_SET_INFORMATION_CLASS, *PHAL_SET_INFORMATION_CLASS;
301 typedef struct _BUS_HANDLER *PBUS_HANDLER;
302 typedef struct _DEVICE_HANDLER_OBJECT *PDEVICE_HANDLER_OBJECT;
305 typedef BOOLEAN STDCALL_FUNC
306 (*PHAL_RESET_DISPLAY_PARAMETERS)(ULONG Columns, ULONG Rows);
308 typedef NTSTATUS STDCALL_FUNC
309 (*pHalQuerySystemInformation)(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
312 OUT PULONG ReturnedLength);
315 typedef NTSTATUS STDCALL_FUNC
316 (*pHalSetSystemInformation)(IN HAL_SET_INFORMATION_CLASS InformationClass,
321 typedef NTSTATUS STDCALL_FUNC
322 (*pHalQueryBusSlots)(IN PBUS_HANDLER BusHandler,
324 OUT PULONG SlotNumbers,
325 OUT PULONG ReturnedLength);
328 /* Control codes of HalDeviceControl function */
329 #define BCTL_EJECT 0x0001
330 #define BCTL_QUERY_DEVICE_ID 0x0002
331 #define BCTL_QUERY_DEVICE_UNIQUE_ID 0x0003
332 #define BCTL_QUERY_DEVICE_CAPABILITIES 0x0004
333 #define BCTL_QUERY_DEVICE_RESOURCES 0x0005
334 #define BCTL_QUERY_DEVICE_RESOURCE_REQUIREMENTS 0x0006
335 #define BCTL_QUERY_EJECT 0x0007
336 #define BCTL_SET_LOCK 0x0008
337 #define BCTL_SET_POWER 0x0009
338 #define BCTL_SET_RESUME 0x000A
339 #define BCTL_SET_DEVICE_RESOURCES 0x000B
341 /* Defines for BCTL structures */
344 BOOLEAN PowerSupported;
345 BOOLEAN ResumeSupported;
346 BOOLEAN LockSupported;
347 BOOLEAN EjectSupported;
349 } BCTL_DEVICE_CAPABILITIES, *PBCTL_DEVICE_CAPABILITIES;
352 typedef struct _DEVICE_CONTROL_CONTEXT
355 PDEVICE_HANDLER_OBJECT DeviceHandler;
356 PDEVICE_OBJECT DeviceObject;
361 } DEVICE_CONTROL_CONTEXT, *PDEVICE_CONTROL_CONTEXT;
364 typedef VOID STDCALL_FUNC
365 (*PDEVICE_CONTROL_COMPLETION)(IN PDEVICE_CONTROL_CONTEXT ControlContext);
368 typedef NTSTATUS STDCALL_FUNC
369 (*pHalDeviceControl)(IN PDEVICE_HANDLER_OBJECT DeviceHandler,
370 IN PDEVICE_OBJECT DeviceObject,
371 IN ULONG ControlCode,
372 IN OUT PVOID Buffer OPTIONAL,
373 IN OUT PULONG BufferLength OPTIONAL,
375 IN PDEVICE_CONTROL_COMPLETION CompletionRoutine);
377 typedef VOID FASTCALL
378 (*pHalExamineMBR)(IN PDEVICE_OBJECT DeviceObject,
380 IN ULONG MBRTypeIdentifier,
383 typedef VOID FASTCALL
384 (*pHalIoAssignDriveLetters)(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
385 IN PSTRING NtDeviceName,
386 OUT PUCHAR NtSystemPath,
387 OUT PSTRING NtSystemPathString);
389 typedef NTSTATUS FASTCALL
390 (*pHalIoReadPartitionTable)(IN PDEVICE_OBJECT DeviceObject,
392 IN BOOLEAN ReturnRecognizedPartitions,
393 OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer);
395 typedef NTSTATUS FASTCALL
396 (*pHalIoSetPartitionInformation)(IN PDEVICE_OBJECT DeviceObject,
398 IN ULONG PartitionNumber,
399 IN ULONG PartitionType);
401 typedef NTSTATUS FASTCALL
402 (*pHalIoWritePartitionTable)(IN PDEVICE_OBJECT DeviceObject,
404 IN ULONG SectorsPerTrack,
405 IN ULONG NumberOfHeads,
406 IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer);
408 typedef PBUS_HANDLER FASTCALL
409 (*pHalHandlerForBus)(IN INTERFACE_TYPE InterfaceType,
412 typedef VOID FASTCALL
413 (*pHalReferenceBusHandler)(IN PBUS_HANDLER BusHandler);
416 typedef struct _HAL_DISPATCH
419 pHalQuerySystemInformation HalQuerySystemInformation;
420 pHalSetSystemInformation HalSetSystemInformation;
421 pHalQueryBusSlots HalQueryBusSlots;
422 pHalDeviceControl HalDeviceControl;
423 pHalExamineMBR HalExamineMBR;
424 pHalIoAssignDriveLetters HalIoAssignDriveLetters;
425 pHalIoReadPartitionTable HalIoReadPartitionTable;
426 pHalIoSetPartitionInformation HalIoSetPartitionInformation;
427 pHalIoWritePartitionTable HalIoWritePartitionTable;
428 pHalHandlerForBus HalReferenceHandlerForBus;
429 pHalReferenceBusHandler HalReferenceBusHandler;
430 pHalReferenceBusHandler HalDereferenceBusHandler;
431 } HAL_DISPATCH, *PHAL_DISPATCH;
433 #define HAL_DISPATCH_VERSION 1
436 extern HAL_DISPATCH EXPORTED HalDispatchTable;
438 extern HAL_DISPATCH IMPORTED HalDispatchTable;
442 /* Hal private dispatch table */
444 typedef struct _HAL_PRIVATE_DISPATCH
447 } HAL_PRIVATE_DISPATCH, *PHAL_PRIVATE_DISPATCH;
449 #define HAL_PRIVATE_DISPATCH_VERSION 1
453 extern HAL_PRIVATE_DISPATCH EXPORTED HalPrivateDispatchTable;
455 extern HAL_PRIVATE_DISPATCH IMPORTED HalPrivateDispatchTable;
461 * Kernel debugger section
464 typedef struct _KD_PORT_INFORMATION
469 } KD_PORT_INFORMATION, *PKD_PORT_INFORMATION;
473 extern ULONG EXPORTED KdComPortInUse;
475 extern ULONG IMPORTED KdComPortInUse;
478 #endif /* __INCLUDE_DDK_HALTYPES_H */