include/ddk/haltypes.h

   1 /* $Id$
   2  *
   3  * COPYRIGHT:                See COPYING in the top level directory
   4  * PROJECT:                  ReactOS kernel
   5  * FILE:                     include/ddk/haltypes.h
   6  * PURPOSE:                  HAL provided defintions for device drivers
   7  * PROGRAMMER:               David Welch (welch@mcmail.com)
   8  * REVISION HISTORY:
   9  *              23/06/98:   Taken from linux system.h
  10  */
  11
  12
  13 #ifndef __INCLUDE_DDK_HALTYPES_H
  14 #define __INCLUDE_DDK_HALTYPES_H
  15
  16
  17 /* HalReturnToFirmware */
  18 #define FIRMWARE_HALT   1
  19 #define FIRMWARE_REBOOT 3
  20
  21 enum
  22 {
  23    DEVICE_DESCRIPTION_VERSION,
  24    DEVICE_DESCRIPTION_VERSION1,
  25 };
  26
  27 typedef ULONG DMA_WIDTH;
  28 typedef ULONG DMA_SPEED;
  29
  30 /*
  31  * PURPOSE: Types for HalGetBusData
  32  */
  33 typedef enum _BUS_DATA_TYPE
  34 {
  35    ConfigurationSpaceUndefined = -1,
  36    Cmos,
  37    EisaConfiguration,
  38    Pos,
  39    CbusConfiguration,
  40    PCIConfiguration,
  41    VMEConfiguration,
  42    NuBusConfiguration,
  43    PCMCIAConfiguration,
  44    MPIConfiguration,
  45    MPSAConfiguration,
  46    PNPISAConfiguration,
  47    MaximumBusDataType,
  48 } BUS_DATA_TYPE, *PBUS_DATA_TYPE;
  49
  50 typedef struct _DEVICE_DESCRIPTION
  51 {
  52   ULONG Version;
  53   BOOLEAN Master;
  54   BOOLEAN ScatterGather;
  55   BOOLEAN DemandMode;
  56   BOOLEAN AutoInitialize;
  57   BOOLEAN Dma32BitAddress;
  58   BOOLEAN IgnoreCount;
  59   BOOLEAN Reserved1;
  60   BOOLEAN Reserved2;
  61   ULONG BusNumber;
  62   ULONG DmaChannel;
  63   INTERFACE_TYPE InterfaceType;
  64   DMA_WIDTH DmaWidth;
  65   DMA_SPEED DmaSpeed;
  66   ULONG MaximumLength;
  67   ULONG DmaPort;
  68 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
  69
  70
  71 /* PCI bus definitions */
  72
  73 #define PCI_TYPE0_ADDRESSES     6
  74 #define PCI_TYPE1_ADDRESSES     2
  75 #define PCI_TYPE2_ADDRESSES     5
  76
  77 typedef struct _PCI_COMMON_CONFIG
  78 {
  79   USHORT VendorID;              /* read-only */
  80   USHORT DeviceID;              /* read-only */
  81   USHORT Command;
  82   USHORT Status;
  83   UCHAR  RevisionID;            /* read-only */
  84   UCHAR  ProgIf;                /* read-only */
  85   UCHAR  SubClass;              /* read-only */
  86   UCHAR  BaseClass;             /* read-only */
  87   UCHAR  CacheLineSize;         /* read-only */
  88   UCHAR  LatencyTimer;          /* read-only */
  89   UCHAR  HeaderType;            /* read-only */
  90   UCHAR  BIST;
  91   union
  92     {
  93       struct _PCI_HEADER_TYPE_0
  94         {
  95           ULONG  BaseAddresses[PCI_TYPE0_ADDRESSES];
  96           ULONG  CIS;
  97           USHORT SubVendorID;
  98           USHORT SubSystemID;
  99           ULONG  ROMBaseAddress;
 100           ULONG  Reserved2[2];
 101
 102           UCHAR  InterruptLine;
 103           UCHAR  InterruptPin;          /* read-only */
 104           UCHAR  MinimumGrant;          /* read-only */
 105           UCHAR  MaximumLatency;        /* read-only */
 106         } type0;
 107
 108       /* PCI to PCI Bridge */
 109       struct _PCI_HEADER_TYPE_1
 110         {
 111           ULONG  BaseAddresses[PCI_TYPE1_ADDRESSES];
 112           UCHAR  PrimaryBus;
 113           UCHAR  SecondaryBus;
 114           UCHAR  SubordinateBus;
 115           UCHAR  SecondaryLatency;
 116           UCHAR  IOBase;
 117           UCHAR  IOLimit;
 118           USHORT SecondaryStatus;
 119           USHORT MemoryBase;
 120           USHORT MemoryLimit;
 121           USHORT PrefetchBase;
 122           USHORT PrefetchLimit;
 123           ULONG  PrefetchBaseUpper32;
 124           ULONG  PrefetchLimitUpper32;
 125           USHORT IOBaseUpper16;
 126           USHORT IOLimitUpper16;
 127           UCHAR  CapabilitiesPtr;
 128           UCHAR  Reserved1[3];
 129           ULONG  ROMBaseAddress;
 130           UCHAR  InterruptLine;
 131           UCHAR  InterruptPin;
 132           USHORT BridgeControl;
 133         } type1;
 134
 135       /* PCI to CARDBUS Bridge */
 136       struct _PCI_HEADER_TYPE_2
 137         {
 138           ULONG  SocketRegistersBaseAddress;
 139           UCHAR  CapabilitiesPtr;
 140           UCHAR  Reserved;
 141           USHORT SecondaryStatus;
 142           UCHAR  PrimaryBus;
 143           UCHAR  SecondaryBus;
 144           UCHAR  SubordinateBus;
 145           UCHAR  SecondaryLatency;
 146           struct
 147             {
 148               ULONG Base;
 149               ULONG Limit;
 150             } Range[PCI_TYPE2_ADDRESSES-1];
 151           UCHAR  InterruptLine;
 152           UCHAR  InterruptPin;
 153           USHORT BridgeControl;
 154         } type2;
 155     } u;
 156   UCHAR DeviceSpecific[192];
 157 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
 158
 159 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
 160
 161 #define PCI_MAX_DEVICES                     32
 162 #define PCI_MAX_FUNCTION                    8
 163
 164 #define PCI_INVALID_VENDORID                0xFFFF
 165
 166
 167 /* Bit encodings for  PCI_COMMON_CONFIG.HeaderType */
 168
 169 #define PCI_MULTIFUNCTION                   0x80
 170 #define PCI_DEVICE_TYPE                     0x00
 171 #define PCI_BRIDGE_TYPE                     0x01
 172
 173
 174 /* Bit encodings for PCI_COMMON_CONFIG.Command */
 175
 176 #define PCI_ENABLE_IO_SPACE                 0x0001
 177 #define PCI_ENABLE_MEMORY_SPACE             0x0002
 178 #define PCI_ENABLE_BUS_MASTER               0x0004
 179 #define PCI_ENABLE_SPECIAL_CYCLES           0x0008
 180 #define PCI_ENABLE_WRITE_AND_INVALIDATE     0x0010
 181 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE   0x0020
 182 #define PCI_ENABLE_PARITY                   0x0040
 183 #define PCI_ENABLE_WAIT_CYCLE               0x0080
 184 #define PCI_ENABLE_SERR                     0x0100
 185 #define PCI_ENABLE_FAST_BACK_TO_BACK        0x0200
 186
 187
 188 /* Bit encodings for PCI_COMMON_CONFIG.Status */
 189
 190 #define PCI_STATUS_FAST_BACK_TO_BACK        0x0080
 191 #define PCI_STATUS_DATA_PARITY_DETECTED     0x0100
 192 #define PCI_STATUS_DEVSEL                   0x0600  /* 2 bits wide */
 193 #define PCI_STATUS_SIGNALED_TARGET_ABORT    0x0800
 194 #define PCI_STATUS_RECEIVED_TARGET_ABORT    0x1000
 195 #define PCI_STATUS_RECEIVED_MASTER_ABORT    0x2000
 196 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR    0x4000
 197 #define PCI_STATUS_DETECTED_PARITY_ERROR    0x8000
 198
 199
 200 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
 201
 202 #define PCI_ADDRESS_IO_SPACE                0x00000001
 203 #define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000006
 204 #define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
 205
 206 #define PCI_TYPE_32BIT      0
 207 #define PCI_TYPE_20BIT      2
 208 #define PCI_TYPE_64BIT      4
 209
 210
 211 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
 212
 213 #define PCI_ROMADDRESS_ENABLED              0x00000001
 214
 215
 216 typedef struct _PCI_SLOT_NUMBER
 217 {
 218   union
 219     {
 220       struct
 221         {
 222           ULONG DeviceNumber:5;
 223           ULONG FunctionNumber:3;
 224           ULONG Reserved:24;
 225         } bits;
 226       ULONG AsULONG;
 227     } u;
 228 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
 229
 230
 231 /* MicroChannel bus data */
 232
 233 typedef struct _CM_MCA_POS_DATA
 234 {
 235   USHORT AdapterId;
 236   UCHAR PosData1;
 237   UCHAR PosData2;
 238   UCHAR PosData3;
 239   UCHAR PosData4;
 240 } CM_MCA_POS_DATA, *PCM_MCA_POS_DATA;
 241
 242
 243 /* Hal dispatch table */
 244
 245 typedef enum _HAL_QUERY_INFORMATION_CLASS
 246 {
 247   HalInstalledBusInformation,
 248   HalProfileSourceInformation,
 249   HalSystemDockInformation,
 250   HalPowerInformation,
 251   HalProcessorSpeedInformation,
 252   HalCallbackInformation,
 253   HalMapRegisterInformation,
 254   HalMcaLogInformation,
 255   HalFrameBufferCachingInformation,
 256   HalDisplayBiosInformation
 257   /* information levels >= 0x8000000 reserved for OEM use */
 258 } HAL_QUERY_INFORMATION_CLASS, *PHAL_QUERY_INFORMATION_CLASS;
 259
 260
 261 typedef enum _HAL_SET_INFORMATION_CLASS
 262 {
 263   HalProfileSourceInterval,
 264   HalProfileSourceInterruptHandler,
 265   HalMcaRegisterDriver
 266 } HAL_SET_INFORMATION_CLASS, *PHAL_SET_INFORMATION_CLASS;
 267
 268
 269 typedef struct _BUS_HANDLER *PBUS_HANDLER;
 270 typedef struct _DEVICE_HANDLER_OBJECT *PDEVICE_HANDLER_OBJECT;
 271
 272
 273 typedef BOOLEAN STDCALL
 274 (*PHAL_RESET_DISPLAY_PARAMETERS)(ULONG Columns, ULONG Rows);
 275
 276 typedef NTSTATUS STDCALL
 277 (*pHalQuerySystemInformation)(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 278                               IN ULONG BufferSize,
 279                               IN OUT PVOID Buffer,
 280                               OUT PULONG ReturnedLength);
 281
 282
 283 typedef NTSTATUS STDCALL
 284 (*pHalSetSystemInformation)(IN HAL_SET_INFORMATION_CLASS InformationClass,
 285                             IN ULONG BufferSize,
 286                             IN PVOID Buffer);
 287
 288
 289 typedef NTSTATUS STDCALL
 290 (*pHalQueryBusSlots)(IN PBUS_HANDLER BusHandler,
 291                      IN ULONG BufferSize,
 292                      OUT PULONG SlotNumbers,
 293                      OUT PULONG ReturnedLength);
 294
 295
 296 /* Control codes of HalDeviceControl function */
 297 #define BCTL_EJECT                              0x0001
 298 #define BCTL_QUERY_DEVICE_ID                    0x0002
 299 #define BCTL_QUERY_DEVICE_UNIQUE_ID             0x0003
 300 #define BCTL_QUERY_DEVICE_CAPABILITIES          0x0004
 301 #define BCTL_QUERY_DEVICE_RESOURCES             0x0005
 302 #define BCTL_QUERY_DEVICE_RESOURCE_REQUIREMENTS 0x0006
 303 #define BCTL_QUERY_EJECT                            0x0007
 304 #define BCTL_SET_LOCK                               0x0008
 305 #define BCTL_SET_POWER                              0x0009
 306 #define BCTL_SET_RESUME                             0x000A
 307 #define BCTL_SET_DEVICE_RESOURCES                   0x000B
 308
 309 /* Defines for BCTL structures */
 310 typedef struct
 311 {
 312   BOOLEAN PowerSupported;
 313   BOOLEAN ResumeSupported;
 314   BOOLEAN LockSupported;
 315   BOOLEAN EjectSupported;
 316   BOOLEAN Removable;
 317 } BCTL_DEVICE_CAPABILITIES, *PBCTL_DEVICE_CAPABILITIES;
 318
 319
 320 typedef struct _DEVICE_CONTROL_CONTEXT
 321 {
 322   NTSTATUS Status;
 323   PDEVICE_HANDLER_OBJECT DeviceHandler;
 324   PDEVICE_OBJECT DeviceObject;
 325   ULONG ControlCode;
 326   PVOID Buffer;
 327   PULONG BufferLength;
 328   PVOID Context;
 329 } DEVICE_CONTROL_CONTEXT, *PDEVICE_CONTROL_CONTEXT;
 330
 331
 332 typedef VOID STDCALL
 333 (*PDEVICE_CONTROL_COMPLETION)(IN PDEVICE_CONTROL_CONTEXT ControlContext);
 334
 335
 336 typedef NTSTATUS STDCALL
 337 (*pHalDeviceControl)(IN PDEVICE_HANDLER_OBJECT DeviceHandler,
 338                      IN PDEVICE_OBJECT DeviceObject,
 339                      IN ULONG ControlCode,
 340                      IN OUT PVOID Buffer OPTIONAL,
 341                      IN OUT PULONG BufferLength OPTIONAL,
 342                      IN PVOID Context,
 343                      IN PDEVICE_CONTROL_COMPLETION CompletionRoutine);
 344
 345 typedef VOID FASTCALL
 346 (*pHalExamineMBR)(IN PDEVICE_OBJECT DeviceObject,
 347                   IN ULONG SectorSize,
 348                   IN ULONG MBRTypeIdentifier,
 349                   OUT PVOID *Buffer);
 350
 351 typedef VOID FASTCALL
 352 (*pHalIoAssignDriveLetters)(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 353                             IN PSTRING NtDeviceName,
 354                             OUT PUCHAR NtSystemPath,
 355                             OUT PSTRING NtSystemPathString);
 356
 357 typedef NTSTATUS FASTCALL
 358 (*pHalIoReadPartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 359                             IN ULONG SectorSize,
 360                             IN BOOLEAN ReturnRecognizedPartitions,
 361                             OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer);
 362
 363 typedef NTSTATUS FASTCALL
 364 (*pHalIoSetPartitionInformation)(IN PDEVICE_OBJECT DeviceObject,
 365                                  IN ULONG SectorSize,
 366                                  IN ULONG PartitionNumber,
 367                                  IN ULONG PartitionType);
 368
 369 typedef NTSTATUS FASTCALL
 370 (*pHalIoWritePartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 371                              IN ULONG SectorSize,
 372                              IN ULONG SectorsPerTrack,
 373                              IN ULONG NumberOfHeads,
 374                              IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer);
 375
 376 typedef PBUS_HANDLER FASTCALL
 377 (*pHalHandlerForBus)(IN INTERFACE_TYPE InterfaceType,
 378                      IN ULONG BusNumber);
 379
 380 typedef VOID FASTCALL
 381 (*pHalReferenceBusHandler)(IN PBUS_HANDLER BusHandler);
 382
 383
 384 typedef struct _HAL_DISPATCH
 385 {
 386   ULONG                         Version;
 387   pHalQuerySystemInformation    HalQuerySystemInformation;
 388   pHalSetSystemInformation      HalSetSystemInformation;
 389   pHalQueryBusSlots             HalQueryBusSlots;
 390   pHalDeviceControl             HalDeviceControl;
 391   pHalExamineMBR                HalExamineMBR;
 392   pHalIoAssignDriveLetters      HalIoAssignDriveLetters;
 393   pHalIoReadPartitionTable      HalIoReadPartitionTable;
 394   pHalIoSetPartitionInformation HalIoSetPartitionInformation;
 395   pHalIoWritePartitionTable     HalIoWritePartitionTable;
 396   pHalHandlerForBus             HalReferenceHandlerForBus;
 397   pHalReferenceBusHandler       HalReferenceBusHandler;
 398   pHalReferenceBusHandler       HalDereferenceBusHandler;
 399 } HAL_DISPATCH, *PHAL_DISPATCH;
 400
 401 #define HAL_DISPATCH_VERSION 1
 402
 403 #ifdef __NTOSKRNL__
 404 extern HAL_DISPATCH EXPORTED HalDispatchTable;
 405 #else
 406 extern HAL_DISPATCH IMPORTED HalDispatchTable;
 407 #endif
 408
 409
 410 /* Hal private dispatch table */
 411
 412 typedef struct _HAL_PRIVATE_DISPATCH
 413 {
 414   ULONG Version;
 415 } HAL_PRIVATE_DISPATCH, *PHAL_PRIVATE_DISPATCH;
 416
 417 #define HAL_PRIVATE_DISPATCH_VERSION 1
 418
 419
 420 #ifdef __NTOSKRNL__
 421 extern HAL_PRIVATE_DISPATCH EXPORTED HalPrivateDispatchTable;
 422 #else
 423 extern HAL_PRIVATE_DISPATCH IMPORTED HalPrivateDispatchTable;
 424 #endif
 425
 426
 427
 428 /*
 429  * Kernel debugger section
 430  */
 431
 432 typedef struct _KD_PORT_INFORMATION
 433 {
 434   ULONG ComPort;
 435   ULONG BaudRate;
 436   ULONG BaseAddress;
 437 } KD_PORT_INFORMATION, *PKD_PORT_INFORMATION;
 438
 439
 440 #ifdef __NTHAL__
 441 extern ULONG EXPORTED KdComPortInUse;
 442 #else
 443 extern ULONG IMPORTED KdComPortInUse;
 444 #endif
 445
 446 #endif /* __INCLUDE_DDK_HALTYPES_H */
 447
 448 /* EOF */