include/ddk/haltypes.h

   1 /* $Id$
   2  *
   3  * COPYRIGHT:                See COPYING in the top level directory
   4  * PROJECT:                  ReactOS kernel
   5  * FILE:                     include/ddk/haltypes.h
   6  * PURPOSE:                  HAL provided defintions for device drivers
   7  * PROGRAMMER:               David Welch (welch@mcmail.com)
   8  * REVISION HISTORY:
   9  *              23/06/98:   Taken from linux system.h
  10  */
  11
  12
  13 #ifndef __INCLUDE_DDK_HALTYPES_H
  14 #define __INCLUDE_DDK_HALTYPES_H
  15
  16
  17 /* HalReturnToFirmware */
  18 #define FIRMWARE_HALT   1
  19 #define FIRMWARE_REBOOT 3
  20
  21 enum
  22 {
  23    DEVICE_DESCRIPTION_VERSION,
  24    DEVICE_DESCRIPTION_VERSION1,
  25 };
  26
  27 typedef ULONG DMA_WIDTH;
  28 typedef ULONG DMA_SPEED;
  29
  30 /*
  31  * PURPOSE: Types for HalGetBusData
  32  */
  33 typedef enum _BUS_DATA_TYPE
  34 {
  35    ConfigurationSpaceUndefined = -1,
  36    Cmos,
  37    EisaConfiguration,
  38    Pos,
  39    CbusConfiguration,
  40    PCIConfiguration,
  41    VMEConfiguration,
  42    NuBusConfiguration,
  43    PCMCIAConfiguration,
  44    MPIConfiguration,
  45    MPSAConfiguration,
  46    PNPISAConfiguration,
  47    MaximumBusDataType,
  48 } BUS_DATA_TYPE, *PBUS_DATA_TYPE;
  49
  50 typedef struct _DEVICE_DESCRIPTION
  51 {
  52   ULONG Version;
  53   BOOLEAN Master;
  54   BOOLEAN ScatterGather;
  55   BOOLEAN DemandMode;
  56   BOOLEAN AutoInitialize;
  57   BOOLEAN Dma32BitAddress;
  58   BOOLEAN IgnoreCount;
  59   BOOLEAN Reserved1;
  60   BOOLEAN Reserved2;
  61   ULONG BusNumber;
  62   ULONG DmaChannel;
  63   INTERFACE_TYPE InterfaceType;
  64   DMA_WIDTH DmaWidth;
  65   DMA_SPEED DmaSpeed;
  66   ULONG MaximumLength;
  67   ULONG DmaPort;
  68 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
  69
  70
  71 /* PCI bus definitions */
  72
  73 #define PCI_TYPE0_ADDRESSES     6
  74 #define PCI_TYPE1_ADDRESSES     2
  75 #define PCI_TYPE2_ADDRESSES     5
  76
  77 typedef struct _PCI_COMMON_CONFIG
  78 {
  79   USHORT VendorID;              /* read-only */
  80   USHORT DeviceID;              /* read-only */
  81   USHORT Command;
  82   USHORT Status;
  83   UCHAR  RevisionID;            /* read-only */
  84   UCHAR  ProgIf;                /* read-only */
  85   UCHAR  SubClass;              /* read-only */
  86   UCHAR  BaseClass;             /* read-only */
  87   UCHAR  CacheLineSize;         /* read-only */
  88   UCHAR  LatencyTimer;          /* read-only */
  89   UCHAR  HeaderType;            /* read-only */
  90   UCHAR  BIST;
  91   union
  92     {
  93       struct _PCI_HEADER_TYPE_0
  94         {
  95           ULONG  BaseAddresses[PCI_TYPE0_ADDRESSES];
  96           ULONG  CIS;
  97           USHORT SubVendorID;
  98           USHORT SubSystemID;
  99           ULONG  ROMBaseAddress;
 100           ULONG  Reserved2[2];
 101
 102           UCHAR  InterruptLine;
 103           UCHAR  InterruptPin;          /* read-only */
 104           UCHAR  MinimumGrant;          /* read-only */
 105           UCHAR  MaximumLatency;        /* read-only */
 106         } type0;
 107
 108       /* PCI to PCI Bridge */
 109       struct _PCI_HEADER_TYPE_1
 110         {
 111           ULONG  BaseAddresses[PCI_TYPE1_ADDRESSES];
 112           UCHAR  PrimaryBus;
 113           UCHAR  SecondaryBus;
 114           UCHAR  SubordinateBus;
 115           UCHAR  SecondaryLatency;
 116           UCHAR  IOBase;
 117           UCHAR  IOLimit;
 118           USHORT SecondaryStatus;
 119           USHORT MemoryBase;
 120           USHORT MemoryLimit;
 121           USHORT PrefetchBase;
 122           USHORT PrefetchLimit;
 123           ULONG  PrefetchBaseUpper32;
 124           ULONG  PrefetchLimitUpper32;
 125           USHORT IOBaseUpper16;
 126           USHORT IOLimitUpper16;
 127           UCHAR  CapabilitiesPtr;
 128           UCHAR  Reserved1[3];
 129           ULONG  ROMBaseAddress;
 130           UCHAR  InterruptLine;
 131           UCHAR  InterruptPin;
 132           USHORT BridgeControl;
 133         } type1;
 134
 135       /* PCI to CARDBUS Bridge */
 136       struct _PCI_HEADER_TYPE_2
 137         {
 138           ULONG  SocketRegistersBaseAddress;
 139           UCHAR  CapabilitiesPtr;
 140           UCHAR  Reserved;
 141           USHORT SecondaryStatus;
 142           UCHAR  PrimaryBus;
 143           UCHAR  SecondaryBus;
 144           UCHAR  SubordinateBus;
 145           UCHAR  SecondaryLatency;
 146           struct
 147             {
 148               ULONG Base;
 149               ULONG Limit;
 150             } Range[PCI_TYPE2_ADDRESSES-1];
 151           UCHAR  InterruptLine;
 152           UCHAR  InterruptPin;
 153           USHORT BridgeControl;
 154         } type2;
 155     } u;
 156   UCHAR DeviceSpecific[192];
 157 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
 158
 159 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
 160
 161 #define PCI_MAX_DEVICES                     32
 162 #define PCI_MAX_FUNCTION                    8
 163
 164 #define PCI_INVALID_VENDORID                0xFFFF
 165
 166
 167 /* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
 168
 169 #define PCI_MULTIFUNCTION                   0x80
 170 #define PCI_DEVICE_TYPE                     0x00
 171 #define PCI_BRIDGE_TYPE                     0x01
 172
 173
 174 /* Bit encodings for PCI_COMMON_CONFIG.Command */
 175
 176 #define PCI_ENABLE_IO_SPACE                 0x0001
 177 #define PCI_ENABLE_MEMORY_SPACE             0x0002
 178 #define PCI_ENABLE_BUS_MASTER               0x0004
 179 #define PCI_ENABLE_SPECIAL_CYCLES           0x0008
 180 #define PCI_ENABLE_WRITE_AND_INVALIDATE     0x0010
 181 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE   0x0020
 182 #define PCI_ENABLE_PARITY                   0x0040
 183 #define PCI_ENABLE_WAIT_CYCLE               0x0080
 184 #define PCI_ENABLE_SERR                     0x0100
 185 #define PCI_ENABLE_FAST_BACK_TO_BACK        0x0200
 186
 187
 188 /* Bit encodings for PCI_COMMON_CONFIG.Status */
 189
 190 #define PCI_STATUS_FAST_BACK_TO_BACK        0x0080
 191 #define PCI_STATUS_DATA_PARITY_DETECTED     0x0100
 192 #define PCI_STATUS_DEVSEL                   0x0600  /* 2 bits wide */
 193 #define PCI_STATUS_SIGNALED_TARGET_ABORT    0x0800
 194 #define PCI_STATUS_RECEIVED_TARGET_ABORT    0x1000
 195 #define PCI_STATUS_RECEIVED_MASTER_ABORT    0x2000
 196 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR    0x4000
 197 #define PCI_STATUS_DETECTED_PARITY_ERROR    0x8000
 198
 199
 200 /* PCI device classes */
 201
 202 #define PCI_CLASS_PRE_20                    0x00
 203 #define PCI_CLASS_MASS_STORAGE_CTLR         0x01
 204 #define PCI_CLASS_NETWORK_CTLR              0x02
 205 #define PCI_CLASS_DISPLAY_CTLR              0x03
 206 #define PCI_CLASS_MULTIMEDIA_DEV            0x04
 207 #define PCI_CLASS_MEMORY_CTLR               0x05
 208 #define PCI_CLASS_BRIDGE_DEV                0x06
 209 #define PCI_CLASS_SIMPLE_COMMS_CTLR         0x07
 210 #define PCI_CLASS_BASE_SYSTEM_DEV           0x08
 211 #define PCI_CLASS_INPUT_DEV                 0x09
 212 #define PCI_CLASS_DOCKING_STATION           0x0a
 213 #define PCI_CLASS_PROCESSOR                 0x0b
 214 #define PCI_CLASS_SERIAL_BUS_CTLR           0x0c
 215
 216
 217 /* PCI device subclasses for class 1 (mass storage controllers)*/
 218
 219 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR      0x00
 220 #define PCI_SUBCLASS_MSC_IDE_CTLR           0x01
 221 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR        0x02
 222 #define PCI_SUBCLASS_MSC_IPI_CTLR           0x03
 223 #define PCI_SUBCLASS_MSC_RAID_CTLR          0x04
 224 #define PCI_SUBCLASS_MSC_OTHER              0x80
 225
 226
 227 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
 228
 229 #define PCI_ADDRESS_IO_SPACE                0x00000001
 230 #define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000006
 231 #define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
 232
 233 #define PCI_ADDRESS_IO_ADDRESS_MASK         0xfffffffc
 234 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK     0xfffffff0
 235 #define PCI_ADDRESS_ROM_ADDRESS_MASK        0xfffff800
 236
 237 #define PCI_TYPE_32BIT      0
 238 #define PCI_TYPE_20BIT      2
 239 #define PCI_TYPE_64BIT      4
 240
 241
 242 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
 243
 244 #define PCI_ROMADDRESS_ENABLED              0x00000001
 245
 246
 247
 248 typedef struct _PCI_SLOT_NUMBER
 249 {
 250   union
 251     {
 252       struct
 253         {
 254           ULONG DeviceNumber:5;
 255           ULONG FunctionNumber:3;
 256           ULONG Reserved:24;
 257         } bits;
 258       ULONG AsULONG;
 259     } u;
 260 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
 261
 262
 263 /* Hal dispatch table */
 264
 265 typedef enum _HAL_QUERY_INFORMATION_CLASS
 266 {
 267   HalInstalledBusInformation,
 268   HalProfileSourceInformation,
 269   HalSystemDockInformation,
 270   HalPowerInformation,
 271   HalProcessorSpeedInformation,
 272   HalCallbackInformation,
 273   HalMapRegisterInformation,
 274   HalMcaLogInformation,
 275   HalFrameBufferCachingInformation,
 276   HalDisplayBiosInformation
 277   /* information levels >= 0x8000000 reserved for OEM use */
 278 } HAL_QUERY_INFORMATION_CLASS, *PHAL_QUERY_INFORMATION_CLASS;
 279
 280
 281 typedef enum _HAL_SET_INFORMATION_CLASS
 282 {
 283   HalProfileSourceInterval,
 284   HalProfileSourceInterruptHandler,
 285   HalMcaRegisterDriver
 286 } HAL_SET_INFORMATION_CLASS, *PHAL_SET_INFORMATION_CLASS;
 287
 288
 289 typedef struct _BUS_HANDLER *PBUS_HANDLER;
 290 typedef struct _DEVICE_HANDLER_OBJECT *PDEVICE_HANDLER_OBJECT;
 291
 292
 293 typedef BOOLEAN STDCALL_FUNC
 294 (*PHAL_RESET_DISPLAY_PARAMETERS)(ULONG Columns, ULONG Rows);
 295
 296 typedef NTSTATUS STDCALL_FUNC
 297 (*pHalQuerySystemInformation)(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 298                               IN ULONG BufferSize,
 299                               IN OUT PVOID Buffer,
 300                               OUT PULONG ReturnedLength);
 301
 302
 303 typedef NTSTATUS STDCALL_FUNC
 304 (*pHalSetSystemInformation)(IN HAL_SET_INFORMATION_CLASS InformationClass,
 305                             IN ULONG BufferSize,
 306                             IN PVOID Buffer);
 307
 308
 309 typedef NTSTATUS STDCALL_FUNC
 310 (*pHalQueryBusSlots)(IN PBUS_HANDLER BusHandler,
 311                      IN ULONG BufferSize,
 312                      OUT PULONG SlotNumbers,
 313                      OUT PULONG ReturnedLength);
 314
 315
 316 /* Control codes of HalDeviceControl function */
 317 #define BCTL_EJECT                              0x0001
 318 #define BCTL_QUERY_DEVICE_ID                    0x0002
 319 #define BCTL_QUERY_DEVICE_UNIQUE_ID             0x0003
 320 #define BCTL_QUERY_DEVICE_CAPABILITIES          0x0004
 321 #define BCTL_QUERY_DEVICE_RESOURCES             0x0005
 322 #define BCTL_QUERY_DEVICE_RESOURCE_REQUIREMENTS 0x0006
 323 #define BCTL_QUERY_EJECT                            0x0007
 324 #define BCTL_SET_LOCK                               0x0008
 325 #define BCTL_SET_POWER                              0x0009
 326 #define BCTL_SET_RESUME                             0x000A
 327 #define BCTL_SET_DEVICE_RESOURCES                   0x000B
 328
 329 /* Defines for BCTL structures */
 330 typedef struct
 331 {
 332   BOOLEAN PowerSupported;
 333   BOOLEAN ResumeSupported;
 334   BOOLEAN LockSupported;
 335   BOOLEAN EjectSupported;
 336   BOOLEAN Removable;
 337 } BCTL_DEVICE_CAPABILITIES, *PBCTL_DEVICE_CAPABILITIES;
 338
 339
 340 typedef struct _DEVICE_CONTROL_CONTEXT
 341 {
 342   NTSTATUS Status;
 343   PDEVICE_HANDLER_OBJECT DeviceHandler;
 344   PDEVICE_OBJECT DeviceObject;
 345   ULONG ControlCode;
 346   PVOID Buffer;
 347   PULONG BufferLength;
 348   PVOID Context;
 349 } DEVICE_CONTROL_CONTEXT, *PDEVICE_CONTROL_CONTEXT;
 350
 351
 352 typedef VOID STDCALL_FUNC
 353 (*PDEVICE_CONTROL_COMPLETION)(IN PDEVICE_CONTROL_CONTEXT ControlContext);
 354
 355
 356 typedef NTSTATUS STDCALL_FUNC
 357 (*pHalDeviceControl)(IN PDEVICE_HANDLER_OBJECT DeviceHandler,
 358                      IN PDEVICE_OBJECT DeviceObject,
 359                      IN ULONG ControlCode,
 360                      IN OUT PVOID Buffer OPTIONAL,
 361                      IN OUT PULONG BufferLength OPTIONAL,
 362                      IN PVOID Context,
 363                      IN PDEVICE_CONTROL_COMPLETION CompletionRoutine);
 364
 365 typedef VOID FASTCALL
 366 (*pHalExamineMBR)(IN PDEVICE_OBJECT DeviceObject,
 367                   IN ULONG SectorSize,
 368                   IN ULONG MBRTypeIdentifier,
 369                   OUT PVOID *Buffer);
 370
 371 typedef VOID FASTCALL
 372 (*pHalIoAssignDriveLetters)(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 373                             IN PSTRING NtDeviceName,
 374                             OUT PUCHAR NtSystemPath,
 375                             OUT PSTRING NtSystemPathString);
 376
 377 typedef NTSTATUS FASTCALL
 378 (*pHalIoReadPartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 379                             IN ULONG SectorSize,
 380                             IN BOOLEAN ReturnRecognizedPartitions,
 381                             OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer);
 382
 383 typedef NTSTATUS FASTCALL
 384 (*pHalIoSetPartitionInformation)(IN PDEVICE_OBJECT DeviceObject,
 385                                  IN ULONG SectorSize,
 386                                  IN ULONG PartitionNumber,
 387                                  IN ULONG PartitionType);
 388
 389 typedef NTSTATUS FASTCALL
 390 (*pHalIoWritePartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 391                              IN ULONG SectorSize,
 392                              IN ULONG SectorsPerTrack,
 393                              IN ULONG NumberOfHeads,
 394                              IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer);
 395
 396 typedef PBUS_HANDLER FASTCALL
 397 (*pHalHandlerForBus)(IN INTERFACE_TYPE InterfaceType,
 398                      IN ULONG BusNumber);
 399
 400 typedef VOID FASTCALL
 401 (*pHalReferenceBusHandler)(IN PBUS_HANDLER BusHandler);
 402
 403
 404 typedef struct _HAL_DISPATCH
 405 {
 406   ULONG                         Version;
 407   pHalQuerySystemInformation    HalQuerySystemInformation;
 408   pHalSetSystemInformation      HalSetSystemInformation;
 409   pHalQueryBusSlots             HalQueryBusSlots;
 410   pHalDeviceControl             HalDeviceControl;
 411   pHalExamineMBR                HalExamineMBR;
 412   pHalIoAssignDriveLetters      HalIoAssignDriveLetters;
 413   pHalIoReadPartitionTable      HalIoReadPartitionTable;
 414   pHalIoSetPartitionInformation HalIoSetPartitionInformation;
 415   pHalIoWritePartitionTable     HalIoWritePartitionTable;
 416   pHalHandlerForBus             HalReferenceHandlerForBus;
 417   pHalReferenceBusHandler       HalReferenceBusHandler;
 418   pHalReferenceBusHandler       HalDereferenceBusHandler;
 419 } HAL_DISPATCH, *PHAL_DISPATCH;
 420
 421 #ifdef __NTOSKRNL__
 422 extern HAL_DISPATCH EXPORTED HalDispatchTable;
 423 #define HALDISPATCH (&HalDispatchTable)
 424 #else
 425 extern PHAL_DISPATCH IMPORTED HalDispatchTable;
 426 #define HALDISPATCH ((PHAL_DISPATCH)&HalDispatchTable)
 427 #endif
 428
 429 #define HAL_DISPATCH_VERSION            1
 430 #define HalDispatchTableVersion         HALDISPATCH->Version
 431 #define HalQuerySystemInformation       HALDISPATCH->HalQuerySystemInformation
 432 #define HalSetSystemInformation         HALDISPATCH->HalSetSystemInformation
 433 #define HalQueryBusSlots                HALDISPATCH->HalQueryBusSlots
 434 #define HalDeviceControl                HALDISPATCH->HalDeviceControl
 435 #define HalExamineMBR                   HALDISPATCH->HalExamineMBR
 436 #define HalIoAssignDriveLetters         HALDISPATCH->HalIoAssignDriveLetters
 437 #define HalIoReadPartitionTable         HALDISPATCH->HalIoReadPartitionTable
 438 #define HalIoSetPartitionInformation    HALDISPATCH->HalIoSetPartitionInformation
 439 #define HalIoWritePartitionTable        HALDISPATCH->HalIoWritePartitionTable
 440 #define HalReferenceHandlerForBus       HALDISPATCH->HalReferenceHandlerForBus
 441 #define HalReferenceBusHandler          HALDISPATCH->HalReferenceBusHandler
 442 #define HalDereferenceBusHandler        HALDISPATCH->HalDereferenceBusHandler
 443
 444
 445 /* Hal private dispatch table */
 446
 447 typedef struct _HAL_PRIVATE_DISPATCH
 448 {
 449   ULONG Version;
 450 } HAL_PRIVATE_DISPATCH, *PHAL_PRIVATE_DISPATCH;
 451
 452
 453 #ifdef __NTOSKRNL__
 454 extern HAL_PRIVATE_DISPATCH EXPORTED HalPrivateDispatchTable;
 455 #else
 456 extern PHAL_PRIVATE_DISPATCH IMPORTED HalPrivateDispatchTable;
 457 #endif
 458
 459 #define HAL_PRIVATE_DISPATCH_VERSION    1
 460
 461
 462
 463 /*
 464  * Kernel debugger section
 465  */
 466
 467 typedef struct _KD_PORT_INFORMATION
 468 {
 469   ULONG ComPort;
 470   ULONG BaudRate;
 471   ULONG BaseAddress;
 472 } KD_PORT_INFORMATION, *PKD_PORT_INFORMATION;
 473
 474
 475 #ifdef __NTHAL__
 476 extern ULONG EXPORTED KdComPortInUse;
 477 #else
 478 extern ULONG IMPORTED KdComPortInUse;
 479 #endif
 480
 481 #endif /* __INCLUDE_DDK_HALTYPES_H */
 482
 483 /* EOF */