include/ntos/haltypes.h

   1 /* $Id$
   2  *
   3  * COPYRIGHT:                See COPYING in the top level directory
   4  * PROJECT:                  ReactOS kernel
   5  * FILE:                     include/ddk/haltypes.h
   6  * PURPOSE:                  HAL provided defintions for device drivers
   7  * PROGRAMMER:               David Welch (welch@mcmail.com)
   8  * REVISION HISTORY:
   9  *              23/06/98:   Taken from linux system.h
  10  */
  11
  12
  13 #ifndef __INCLUDE_NTOS_HALTYPES_H
  14 #define __INCLUDE_NTOS_HALTYPES_H
  15
  16 #ifdef __GNUC__
  17 #define STDCALL_FUNC STDCALL
  18 #else
  19 #define STDCALL_FUNC(a) (__stdcall a )
  20 #endif /*__GNUC__*/
  21
  22 #include "types.h"
  23
  24
  25 /* HalReturnToFirmware */
  26 #define FIRMWARE_HALT   1
  27 #define FIRMWARE_REBOOT 3
  28
  29 #ifndef __USE_W32API
  30
  31 enum
  32 {
  33    DEVICE_DESCRIPTION_VERSION,
  34    DEVICE_DESCRIPTION_VERSION1,
  35 };
  36
  37 typedef ULONG DMA_WIDTH;
  38 typedef ULONG DMA_SPEED;
  39
  40 /*
  41  * PURPOSE: Types for HalGetBusData
  42  */
  43 typedef enum _BUS_DATA_TYPE
  44 {
  45    ConfigurationSpaceUndefined = -1,
  46    Cmos,
  47    EisaConfiguration,
  48    Pos,
  49    CbusConfiguration,
  50    PCIConfiguration,
  51    VMEConfiguration,
  52    NuBusConfiguration,
  53    PCMCIAConfiguration,
  54    MPIConfiguration,
  55    MPSAConfiguration,
  56    PNPISAConfiguration,
  57    MaximumBusDataType,
  58 } BUS_DATA_TYPE, *PBUS_DATA_TYPE;
  59
  60 typedef struct _DEVICE_DESCRIPTION
  61 {
  62   ULONG Version;
  63   BOOLEAN Master;
  64   BOOLEAN ScatterGather;
  65   BOOLEAN DemandMode;
  66   BOOLEAN AutoInitialize;
  67   BOOLEAN Dma32BitAddresses;
  68   BOOLEAN IgnoreCount;
  69   BOOLEAN Reserved1;
  70   BOOLEAN Reserved2;
  71   ULONG BusNumber;
  72   ULONG DmaChannel;
  73   INTERFACE_TYPE InterfaceType;
  74   DMA_WIDTH DmaWidth;
  75   DMA_SPEED DmaSpeed;
  76   ULONG MaximumLength;
  77   ULONG DmaPort;
  78 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
  79
  80
  81 /* PCI bus definitions */
  82
  83 #define PCI_TYPE0_ADDRESSES     6
  84 #define PCI_TYPE1_ADDRESSES     2
  85 #define PCI_TYPE2_ADDRESSES     5
  86
  87 typedef struct _PCI_COMMON_CONFIG
  88 {
  89   USHORT VendorID;              /* read-only */
  90   USHORT DeviceID;              /* read-only */
  91   USHORT Command;
  92   USHORT Status;
  93   UCHAR  RevisionID;            /* read-only */
  94   UCHAR  ProgIf;                /* read-only */
  95   UCHAR  SubClass;              /* read-only */
  96   UCHAR  BaseClass;             /* read-only */
  97   UCHAR  CacheLineSize;         /* read-only */
  98   UCHAR  LatencyTimer;          /* read-only */
  99   UCHAR  HeaderType;            /* read-only */
 100   UCHAR  BIST;
 101   union
 102     {
 103       struct _PCI_HEADER_TYPE_0
 104         {
 105           ULONG  BaseAddresses[PCI_TYPE0_ADDRESSES];
 106           ULONG  CIS;
 107           USHORT SubVendorID;
 108           USHORT SubSystemID;
 109           ULONG  ROMBaseAddress;
 110           ULONG  Reserved2[2];
 111
 112           UCHAR  InterruptLine;
 113           UCHAR  InterruptPin;          /* read-only */
 114           UCHAR  MinimumGrant;          /* read-only */
 115           UCHAR  MaximumLatency;        /* read-only */
 116         } type0;
 117
 118       /* PCI to PCI Bridge */
 119       struct _PCI_HEADER_TYPE_1
 120         {
 121           ULONG  BaseAddresses[PCI_TYPE1_ADDRESSES];
 122           UCHAR  PrimaryBus;
 123           UCHAR  SecondaryBus;
 124           UCHAR  SubordinateBus;
 125           UCHAR  SecondaryLatency;
 126           UCHAR  IOBase;
 127           UCHAR  IOLimit;
 128           USHORT SecondaryStatus;
 129           USHORT MemoryBase;
 130           USHORT MemoryLimit;
 131           USHORT PrefetchBase;
 132           USHORT PrefetchLimit;
 133           ULONG  PrefetchBaseUpper32;
 134           ULONG  PrefetchLimitUpper32;
 135           USHORT IOBaseUpper16;
 136           USHORT IOLimitUpper16;
 137           UCHAR  CapabilitiesPtr;
 138           UCHAR  Reserved1[3];
 139           ULONG  ROMBaseAddress;
 140           UCHAR  InterruptLine;
 141           UCHAR  InterruptPin;
 142           USHORT BridgeControl;
 143         } type1;
 144
 145       /* PCI to CARDBUS Bridge */
 146       struct _PCI_HEADER_TYPE_2
 147         {
 148           ULONG  SocketRegistersBaseAddress;
 149           UCHAR  CapabilitiesPtr;
 150           UCHAR  Reserved;
 151           USHORT SecondaryStatus;
 152           UCHAR  PrimaryBus;
 153           UCHAR  SecondaryBus;
 154           UCHAR  SubordinateBus;
 155           UCHAR  SecondaryLatency;
 156           struct
 157             {
 158               ULONG Base;
 159               ULONG Limit;
 160             } Range[PCI_TYPE2_ADDRESSES-1];
 161           UCHAR  InterruptLine;
 162           UCHAR  InterruptPin;
 163           USHORT BridgeControl;
 164         } type2;
 165     } u;
 166   UCHAR DeviceSpecific[192];
 167 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
 168
 169 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
 170
 171 #define PCI_MAX_DEVICES                     32
 172 #define PCI_MAX_FUNCTION                    8
 173
 174 #define PCI_INVALID_VENDORID                0xFFFF
 175
 176 /* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
 177
 178 #define PCI_MULTIFUNCTION                   0x80
 179 #define PCI_DEVICE_TYPE                     0x00
 180 #define PCI_BRIDGE_TYPE                     0x01
 181
 182
 183 /* Bit encodings for PCI_COMMON_CONFIG.Command */
 184
 185 #define PCI_ENABLE_IO_SPACE                 0x0001
 186 #define PCI_ENABLE_MEMORY_SPACE             0x0002
 187 #define PCI_ENABLE_BUS_MASTER               0x0004
 188 #define PCI_ENABLE_SPECIAL_CYCLES           0x0008
 189 #define PCI_ENABLE_WRITE_AND_INVALIDATE     0x0010
 190 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE   0x0020
 191 #define PCI_ENABLE_PARITY                   0x0040
 192 #define PCI_ENABLE_WAIT_CYCLE               0x0080
 193 #define PCI_ENABLE_SERR                     0x0100
 194 #define PCI_ENABLE_FAST_BACK_TO_BACK        0x0200
 195
 196
 197 /* Bit encodings for PCI_COMMON_CONFIG.Status */
 198
 199 #define PCI_STATUS_FAST_BACK_TO_BACK        0x0080
 200 #define PCI_STATUS_DATA_PARITY_DETECTED     0x0100
 201 #define PCI_STATUS_DEVSEL                   0x0600  /* 2 bits wide */
 202 #define PCI_STATUS_SIGNALED_TARGET_ABORT    0x0800
 203 #define PCI_STATUS_RECEIVED_TARGET_ABORT    0x1000
 204 #define PCI_STATUS_RECEIVED_MASTER_ABORT    0x2000
 205 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR    0x4000
 206 #define PCI_STATUS_DETECTED_PARITY_ERROR    0x8000
 207
 208
 209 /* PCI device classes */
 210
 211 #define PCI_CLASS_PRE_20                    0x00
 212 #define PCI_CLASS_MASS_STORAGE_CTLR         0x01
 213 #define PCI_CLASS_NETWORK_CTLR              0x02
 214 #define PCI_CLASS_DISPLAY_CTLR              0x03
 215 #define PCI_CLASS_MULTIMEDIA_DEV            0x04
 216 #define PCI_CLASS_MEMORY_CTLR               0x05
 217 #define PCI_CLASS_BRIDGE_DEV                0x06
 218 #define PCI_CLASS_SIMPLE_COMMS_CTLR         0x07
 219 #define PCI_CLASS_BASE_SYSTEM_DEV           0x08
 220 #define PCI_CLASS_INPUT_DEV                 0x09
 221 #define PCI_CLASS_DOCKING_STATION           0x0a
 222 #define PCI_CLASS_PROCESSOR                 0x0b
 223 #define PCI_CLASS_SERIAL_BUS_CTLR           0x0c
 224
 225
 226 /* PCI device subclasses for class 1 (mass storage controllers)*/
 227
 228 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR      0x00
 229 #define PCI_SUBCLASS_MSC_IDE_CTLR           0x01
 230 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR        0x02
 231 #define PCI_SUBCLASS_MSC_IPI_CTLR           0x03
 232 #define PCI_SUBCLASS_MSC_RAID_CTLR          0x04
 233 #define PCI_SUBCLASS_MSC_OTHER              0x80
 234
 235
 236 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
 237
 238 #define PCI_ADDRESS_IO_SPACE                0x00000001
 239 #define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000006
 240 #define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
 241
 242 #define PCI_ADDRESS_IO_ADDRESS_MASK         0xfffffffc
 243 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK     0xfffffff0
 244 #define PCI_ADDRESS_ROM_ADDRESS_MASK        0xfffff800
 245
 246 #define PCI_TYPE_32BIT      0
 247 #define PCI_TYPE_20BIT      2
 248 #define PCI_TYPE_64BIT      4
 249
 250
 251 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
 252
 253 #define PCI_ROMADDRESS_ENABLED              0x00000001
 254
 255
 256
 257 typedef struct _PCI_SLOT_NUMBER
 258 {
 259   union
 260     {
 261       struct
 262         {
 263           ULONG DeviceNumber:5;
 264           ULONG FunctionNumber:3;
 265           ULONG Reserved:24;
 266         } bits;
 267       ULONG AsULONG;
 268     } u;
 269 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
 270
 271 #endif /* __USE_W32API */
 272
 273 /* Hal dispatch table */
 274
 275 typedef enum _HAL_QUERY_INFORMATION_CLASS
 276 {
 277   HalInstalledBusInformation,
 278   HalProfileSourceInformation,
 279   HalSystemDockInformation,
 280   HalPowerInformation,
 281   HalProcessorSpeedInformation,
 282   HalCallbackInformation,
 283   HalMapRegisterInformation,
 284   HalMcaLogInformation,
 285   HalFrameBufferCachingInformation,
 286   HalDisplayBiosInformation
 287   /* information levels >= 0x8000000 reserved for OEM use */
 288 } HAL_QUERY_INFORMATION_CLASS, *PHAL_QUERY_INFORMATION_CLASS;
 289
 290
 291 typedef enum _HAL_SET_INFORMATION_CLASS
 292 {
 293   HalProfileSourceInterval,
 294   HalProfileSourceInterruptHandler,
 295   HalMcaRegisterDriver
 296 } HAL_SET_INFORMATION_CLASS, *PHAL_SET_INFORMATION_CLASS;
 297
 298
 299 typedef struct _BUS_HANDLER *PBUS_HANDLER;
 300 typedef struct _DEVICE_HANDLER_OBJECT *PDEVICE_HANDLER_OBJECT;
 301
 302
 303 typedef BOOLEAN STDCALL_FUNC
 304 (*PHAL_RESET_DISPLAY_PARAMETERS)(ULONG Columns, ULONG Rows);
 305
 306 typedef NTSTATUS STDCALL_FUNC
 307 (*pHalQuerySystemInformation)(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 308                               IN ULONG BufferSize,
 309                               IN OUT PVOID Buffer,
 310                               OUT PULONG ReturnedLength);
 311
 312
 313 typedef NTSTATUS STDCALL_FUNC
 314 (*pHalSetSystemInformation)(IN HAL_SET_INFORMATION_CLASS InformationClass,
 315                             IN ULONG BufferSize,
 316                             IN PVOID Buffer);
 317
 318
 319 typedef NTSTATUS STDCALL_FUNC
 320 (*pHalQueryBusSlots)(IN PBUS_HANDLER BusHandler,
 321                      IN ULONG BufferSize,
 322                      OUT PULONG SlotNumbers,
 323                      OUT PULONG ReturnedLength);
 324
 325
 326 /* Control codes of HalDeviceControl function */
 327 #define BCTL_EJECT                              0x0001
 328 #define BCTL_QUERY_DEVICE_ID                    0x0002
 329 #define BCTL_QUERY_DEVICE_UNIQUE_ID             0x0003
 330 #define BCTL_QUERY_DEVICE_CAPABILITIES          0x0004
 331 #define BCTL_QUERY_DEVICE_RESOURCES             0x0005
 332 #define BCTL_QUERY_DEVICE_RESOURCE_REQUIREMENTS 0x0006
 333 #define BCTL_QUERY_EJECT                            0x0007
 334 #define BCTL_SET_LOCK                               0x0008
 335 #define BCTL_SET_POWER                              0x0009
 336 #define BCTL_SET_RESUME                             0x000A
 337 #define BCTL_SET_DEVICE_RESOURCES                   0x000B
 338
 339 /* Defines for BCTL structures */
 340 typedef struct
 341 {
 342   BOOLEAN PowerSupported;
 343   BOOLEAN ResumeSupported;
 344   BOOLEAN LockSupported;
 345   BOOLEAN EjectSupported;
 346   BOOLEAN Removable;
 347 } BCTL_DEVICE_CAPABILITIES, *PBCTL_DEVICE_CAPABILITIES;
 348
 349
 350 typedef struct _DEVICE_CONTROL_CONTEXT
 351 {
 352   NTSTATUS Status;
 353   PDEVICE_HANDLER_OBJECT DeviceHandler;
 354   PDEVICE_OBJECT DeviceObject;
 355   ULONG ControlCode;
 356   PVOID Buffer;
 357   PULONG BufferLength;
 358   PVOID Context;
 359 } DEVICE_CONTROL_CONTEXT, *PDEVICE_CONTROL_CONTEXT;
 360
 361
 362 typedef VOID STDCALL_FUNC
 363 (*PDEVICE_CONTROL_COMPLETION)(IN PDEVICE_CONTROL_CONTEXT ControlContext);
 364
 365
 366 typedef NTSTATUS STDCALL_FUNC
 367 (*pHalDeviceControl)(IN PDEVICE_HANDLER_OBJECT DeviceHandler,
 368                      IN PDEVICE_OBJECT DeviceObject,
 369                      IN ULONG ControlCode,
 370                      IN OUT PVOID Buffer OPTIONAL,
 371                      IN OUT PULONG BufferLength OPTIONAL,
 372                      IN PVOID Context,
 373                      IN PDEVICE_CONTROL_COMPLETION CompletionRoutine);
 374
 375 typedef VOID FASTCALL
 376 (*pHalExamineMBR)(IN PDEVICE_OBJECT DeviceObject,
 377                   IN ULONG SectorSize,
 378                   IN ULONG MBRTypeIdentifier,
 379                   OUT PVOID *Buffer);
 380
 381 typedef VOID FASTCALL
 382 (*pHalIoAssignDriveLetters)(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 383                             IN PSTRING NtDeviceName,
 384                             OUT PUCHAR NtSystemPath,
 385                             OUT PSTRING NtSystemPathString);
 386
 387 typedef NTSTATUS FASTCALL
 388 (*pHalIoReadPartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 389                             IN ULONG SectorSize,
 390                             IN BOOLEAN ReturnRecognizedPartitions,
 391                             OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer);
 392
 393 typedef NTSTATUS FASTCALL
 394 (*pHalIoSetPartitionInformation)(IN PDEVICE_OBJECT DeviceObject,
 395                                  IN ULONG SectorSize,
 396                                  IN ULONG PartitionNumber,
 397                                  IN ULONG PartitionType);
 398
 399 typedef NTSTATUS FASTCALL
 400 (*pHalIoWritePartitionTable)(IN PDEVICE_OBJECT DeviceObject,
 401                              IN ULONG SectorSize,
 402                              IN ULONG SectorsPerTrack,
 403                              IN ULONG NumberOfHeads,
 404                              IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer);
 405
 406 typedef PBUS_HANDLER FASTCALL
 407 (*pHalHandlerForBus)(IN INTERFACE_TYPE InterfaceType,
 408                      IN ULONG BusNumber);
 409
 410 typedef VOID FASTCALL
 411 (*pHalReferenceBusHandler)(IN PBUS_HANDLER BusHandler);
 412
 413
 414 typedef struct _HAL_DISPATCH
 415 {
 416   ULONG                         Version;
 417   pHalQuerySystemInformation    HalQuerySystemInformation;
 418   pHalSetSystemInformation      HalSetSystemInformation;
 419   pHalQueryBusSlots             HalQueryBusSlots;
 420   pHalDeviceControl             HalDeviceControl;
 421   pHalExamineMBR                HalExamineMBR;
 422   pHalIoAssignDriveLetters      HalIoAssignDriveLetters;
 423   pHalIoReadPartitionTable      HalIoReadPartitionTable;
 424   pHalIoSetPartitionInformation HalIoSetPartitionInformation;
 425   pHalIoWritePartitionTable     HalIoWritePartitionTable;
 426   pHalHandlerForBus             HalReferenceHandlerForBus;
 427   pHalReferenceBusHandler       HalReferenceBusHandler;
 428   pHalReferenceBusHandler       HalDereferenceBusHandler;
 429 } HAL_DISPATCH, *PHAL_DISPATCH;
 430
 431 #ifndef __USE_W32API
 432
 433 #ifdef __NTOSKRNL__
 434 extern HAL_DISPATCH EXPORTED HalDispatchTable;
 435 #else
 436 extern PHAL_DISPATCH IMPORTED HalDispatchTable;
 437 #endif
 438
 439 #endif /* !__USE_W32API */
 440
 441 #ifdef __NTOSKRNL__
 442 #define HALDISPATCH (&HalDispatchTable)
 443 #else
 444 #define HALDISPATCH ((PHAL_DISPATCH)&HalDispatchTable)
 445 #endif
 446
 447
 448 #define HAL_DISPATCH_VERSION            1
 449 #define HalDispatchTableVersion         HALDISPATCH->Version
 450 #define HalQuerySystemInformation       HALDISPATCH->HalQuerySystemInformation
 451 #define HalSetSystemInformation         HALDISPATCH->HalSetSystemInformation
 452 #define HalQueryBusSlots                HALDISPATCH->HalQueryBusSlots
 453 #define HalDeviceControl                HALDISPATCH->HalDeviceControl
 454 #define HalExamineMBR                   HALDISPATCH->HalExamineMBR
 455 #define HalIoAssignDriveLetters         HALDISPATCH->HalIoAssignDriveLetters
 456 #define HalIoReadPartitionTable         HALDISPATCH->HalIoReadPartitionTable
 457 #define HalIoSetPartitionInformation    HALDISPATCH->HalIoSetPartitionInformation
 458 #define HalIoWritePartitionTable        HALDISPATCH->HalIoWritePartitionTable
 459 #define HalReferenceHandlerForBus       HALDISPATCH->HalReferenceHandlerForBus
 460 #define HalReferenceBusHandler          HALDISPATCH->HalReferenceBusHandler
 461 #define HalDereferenceBusHandler        HALDISPATCH->HalDereferenceBusHandler
 462
 463
 464 /* Hal private dispatch table */
 465
 466 typedef struct _HAL_PRIVATE_DISPATCH
 467 {
 468   ULONG Version;
 469 } HAL_PRIVATE_DISPATCH, *PHAL_PRIVATE_DISPATCH;
 470
 471 #ifndef __USE_W32API
 472
 473 #ifdef __NTOSKRNL__
 474 extern HAL_PRIVATE_DISPATCH EXPORTED HalPrivateDispatchTable;
 475 #else
 476 extern PHAL_PRIVATE_DISPATCH IMPORTED HalPrivateDispatchTable;
 477 #endif
 478
 479 #endif /* !__USE_W32API */
 480
 481 #define HAL_PRIVATE_DISPATCH_VERSION    1
 482
 483
 484
 485 /*
 486  * Kernel debugger section
 487  */
 488
 489 typedef struct _KD_PORT_INFORMATION
 490 {
 491   ULONG ComPort;
 492   ULONG BaudRate;
 493   ULONG BaseAddress;
 494 } KD_PORT_INFORMATION, *PKD_PORT_INFORMATION;
 495
 496
 497 #ifdef __NTHAL__
 498 extern ULONG EXPORTED KdComPortInUse;
 499 #else
 500 extern ULONG IMPORTED KdComPortInUse;
 501 #endif
 502
 503 #endif /* __INCLUDE_DDK_HALTYPES_H */
 504
 505 /* EOF */